1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * U-Boot additions
4 *
5 * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
6 */
7
8#include "socfpga_soc64_fit-u-boot.dtsi"
9#include <dt-bindings/clock/n5x-clock.h>
10
11/{
12	memory {
13		#address-cells = <2>;
14		#size-cells = <2>;
15		u-boot,dm-pre-reloc;
16	};
17
18	soc {
19		u-boot,dm-pre-reloc;
20
21		ccu: cache-controller@f7000000 {
22			compatible = "arteris,ncore-ccu";
23			reg = <0xf7000000 0x100900>;
24			u-boot,dm-pre-reloc;
25		};
26
27		clocks {
28			dram_eosc_clk: dram-eosc-clk {
29				#clock-cells = <0>;
30				compatible = "fixed-clock";
31			};
32		};
33
34		memclkmgr: mem-clock-controller@f8040000 {
35			compatible = "intel,n5x-mem-clkmgr";
36			reg = <0xf8040000 0x1000>;
37			#clock-cells = <0>;
38			clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
39		};
40	};
41};
42
43&clkmgr {
44	compatible = "intel,n5x-clkmgr";
45	u-boot,dm-pre-reloc;
46};
47
48&gmac0 {
49	clocks = <&clkmgr N5X_EMAC0_CLK>;
50};
51
52&gmac1 {
53	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
54	clocks = <&clkmgr N5X_EMAC1_CLK>;
55};
56
57&gmac2 {
58	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
59	clocks = <&clkmgr N5X_EMAC2_CLK>;
60};
61
62&i2c0 {
63	clocks = <&clkmgr N5X_L4_SP_CLK>;
64	reset-names = "i2c";
65};
66
67&i2c1 {
68	clocks = <&clkmgr N5X_L4_SP_CLK>;
69	reset-names = "i2c";
70};
71
72&i2c2 {
73	clocks = <&clkmgr N5X_L4_SP_CLK>;
74	reset-names = "i2c";
75};
76
77&i2c3 {
78	clocks = <&clkmgr N5X_L4_SP_CLK>;
79	reset-names = "i2c";
80};
81
82&i2c4 {
83	clocks = <&clkmgr N5X_L4_SP_CLK>;
84	reset-names = "i2c";
85};
86
87&memclkmgr {
88	u-boot,dm-pre-reloc;
89};
90
91&mmc {
92	clocks = <&clkmgr N5X_L4_MP_CLK>,
93		 <&clkmgr N5X_SDMMC_CLK>;
94	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
95};
96
97&pdma {
98	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
99};
100
101&porta {
102	bank-name = "porta";
103};
104
105&portb {
106	bank-name = "portb";
107};
108
109&qspi {
110	u-boot,dm-pre-reloc;
111};
112
113&rst {
114	compatible = "altr,rst-mgr";
115	altr,modrst-offset = <0x20>;
116	u-boot,dm-pre-reloc;
117};
118
119&sdr {
120	compatible = "intel,sdr-ctl-n5x";
121	resets = <&rst DDRSCH_RESET>;
122	clocks = <&memclkmgr>;
123	clock-names = "mem_clk";
124	u-boot,dm-pre-reloc;
125};
126
127&spi0 {
128	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
129};
130
131&spi1 {
132	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
133};
134
135&sysmgr {
136	compatible = "altr,sys-mgr", "syscon";
137	u-boot,dm-pre-reloc;
138};
139
140&timer0 {
141	clocks = <&clkmgr N5X_L4_SP_CLK>;
142};
143
144&timer1 {
145	clocks = <&clkmgr N5X_L4_SP_CLK>;
146};
147
148&timer2 {
149	clocks = <&clkmgr N5X_L4_SP_CLK>;
150};
151
152&timer3 {
153	clocks = <&clkmgr N5X_L4_SP_CLK>;
154};
155
156&uart0 {
157	clocks = <&clkmgr N5X_L4_SP_CLK>;
158	u-boot,dm-pre-reloc;
159};
160
161&uart1 {
162	clocks = <&clkmgr N5X_L4_SP_CLK>;
163};
164
165&usb0 {
166	clocks = <&clkmgr N5X_USB_CLK>;
167	disable-over-current;
168	u-boot,dm-pre-reloc;
169};
170
171&usb1 {
172	clocks = <&clkmgr N5X_USB_CLK>;
173	u-boot,dm-pre-reloc;
174};
175
176&watchdog0 {
177	clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
178	u-boot,dm-pre-reloc;
179};
180
181&watchdog1 {
182	clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
183};
184
185&watchdog2 {
186	clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
187};
188
189&watchdog3 {
190	clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
191};
192