1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 *
5 */
6
7#include "armv7-m.dtsi"
8#include <dt-bindings/clock/stm32fx-clock.h>
9#include <dt-bindings/mfd/stm32f7-rcc.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	clocks {
16		clk_hse: clk-hse {
17			#clock-cells = <0>;
18			compatible = "fixed-clock";
19			clock-frequency = <0>;
20		};
21
22		clk-lse {
23			#clock-cells = <0>;
24			compatible = "fixed-clock";
25			clock-frequency = <32768>;
26		};
27
28		clk-lsi {
29			#clock-cells = <0>;
30			compatible = "fixed-clock";
31			clock-frequency = <32000>;
32		};
33
34		clk_i2s_ckin: clk-i2s-ckin {
35			#clock-cells = <0>;
36			compatible = "fixed-clock";
37			clock-frequency = <48000000>;
38		};
39	};
40
41	soc {
42		timer2: timer@40000000 {
43			compatible = "st,stm32-timer";
44			reg = <0x40000000 0x400>;
45			interrupts = <28>;
46			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
47			status = "disabled";
48		};
49
50		timers2: timers@40000000 {
51			#address-cells = <1>;
52			#size-cells = <0>;
53			compatible = "st,stm32-timers";
54			reg = <0x40000000 0x400>;
55			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
56			clock-names = "int";
57			status = "disabled";
58
59			pwm {
60				compatible = "st,stm32-pwm";
61				#pwm-cells = <3>;
62				status = "disabled";
63			};
64
65			timer@1 {
66				compatible = "st,stm32-timer-trigger";
67				reg = <1>;
68				status = "disabled";
69			};
70		};
71
72		timer3: timer@40000400 {
73			compatible = "st,stm32-timer";
74			reg = <0x40000400 0x400>;
75			interrupts = <29>;
76			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
77			status = "disabled";
78		};
79
80		timers3: timers@40000400 {
81			#address-cells = <1>;
82			#size-cells = <0>;
83			compatible = "st,stm32-timers";
84			reg = <0x40000400 0x400>;
85			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
86			clock-names = "int";
87			status = "disabled";
88
89			pwm {
90				compatible = "st,stm32-pwm";
91				#pwm-cells = <3>;
92				status = "disabled";
93			};
94
95			timer@2 {
96				compatible = "st,stm32-timer-trigger";
97				reg = <2>;
98				status = "disabled";
99			};
100		};
101
102		timer4: timer@40000800 {
103			compatible = "st,stm32-timer";
104			reg = <0x40000800 0x400>;
105			interrupts = <30>;
106			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
107			status = "disabled";
108		};
109
110		timers4: timers@40000800 {
111			#address-cells = <1>;
112			#size-cells = <0>;
113			compatible = "st,stm32-timers";
114			reg = <0x40000800 0x400>;
115			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
116			clock-names = "int";
117			status = "disabled";
118
119			pwm {
120				compatible = "st,stm32-pwm";
121				#pwm-cells = <3>;
122				status = "disabled";
123			};
124
125			timer@3 {
126				compatible = "st,stm32-timer-trigger";
127				reg = <3>;
128				status = "disabled";
129			};
130		};
131
132		timer5: timer@40000c00 {
133			compatible = "st,stm32-timer";
134			reg = <0x40000c00 0x400>;
135			interrupts = <50>;
136			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
137		};
138
139		timers5: timers@40000c00 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			compatible = "st,stm32-timers";
143			reg = <0x40000C00 0x400>;
144			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
145			clock-names = "int";
146			status = "disabled";
147
148			pwm {
149				compatible = "st,stm32-pwm";
150				#pwm-cells = <3>;
151				status = "disabled";
152			};
153
154			timer@4 {
155				compatible = "st,stm32-timer-trigger";
156				reg = <4>;
157				status = "disabled";
158			};
159		};
160
161		timer6: timer@40001000 {
162			compatible = "st,stm32-timer";
163			reg = <0x40001000 0x400>;
164			interrupts = <54>;
165			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
166			status = "disabled";
167		};
168
169		timers6: timers@40001000 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			compatible = "st,stm32-timers";
173			reg = <0x40001000 0x400>;
174			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
175			clock-names = "int";
176			status = "disabled";
177
178			timer@5 {
179				compatible = "st,stm32-timer-trigger";
180				reg = <5>;
181				status = "disabled";
182			};
183		};
184
185		timer7: timer@40001400 {
186			compatible = "st,stm32-timer";
187			reg = <0x40001400 0x400>;
188			interrupts = <55>;
189			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
190			status = "disabled";
191		};
192
193		timers7: timers@40001400 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "st,stm32-timers";
197			reg = <0x40001400 0x400>;
198			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
199			clock-names = "int";
200			status = "disabled";
201
202			timer@6 {
203				compatible = "st,stm32-timer-trigger";
204				reg = <6>;
205				status = "disabled";
206			};
207		};
208
209		timers12: timers@40001800 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "st,stm32-timers";
213			reg = <0x40001800 0x400>;
214			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
215			clock-names = "int";
216			status = "disabled";
217
218			pwm {
219				compatible = "st,stm32-pwm";
220				#pwm-cells = <3>;
221				status = "disabled";
222			};
223
224			timer@11 {
225				compatible = "st,stm32-timer-trigger";
226				reg = <11>;
227				status = "disabled";
228			};
229		};
230
231		timers13: timers@40001c00 {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			compatible = "st,stm32-timers";
235			reg = <0x40001C00 0x400>;
236			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237			clock-names = "int";
238			status = "disabled";
239
240			pwm {
241				compatible = "st,stm32-pwm";
242				#pwm-cells = <3>;
243				status = "disabled";
244			};
245		};
246
247		timers14: timers@40002000 {
248			#address-cells = <1>;
249			#size-cells = <0>;
250			compatible = "st,stm32-timers";
251			reg = <0x40002000 0x400>;
252			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
253			clock-names = "int";
254			status = "disabled";
255
256			pwm {
257				compatible = "st,stm32-pwm";
258				#pwm-cells = <3>;
259				status = "disabled";
260			};
261		};
262
263		rtc: rtc@40002800 {
264			compatible = "st,stm32-rtc";
265			reg = <0x40002800 0x400>;
266			clocks = <&rcc 1 CLK_RTC>;
267			assigned-clocks = <&rcc 1 CLK_RTC>;
268			assigned-clock-parents = <&rcc 1 CLK_LSE>;
269			interrupt-parent = <&exti>;
270			interrupts = <17 1>;
271			st,syscfg = <&pwrcfg 0x00 0x100>;
272			status = "disabled";
273		};
274
275		usart2: serial@40004400 {
276			compatible = "st,stm32f7-uart";
277			reg = <0x40004400 0x400>;
278			interrupts = <38>;
279			clocks = <&rcc 1 CLK_USART2>;
280			status = "disabled";
281		};
282
283		usart3: serial@40004800 {
284			compatible = "st,stm32f7-uart";
285			reg = <0x40004800 0x400>;
286			interrupts = <39>;
287			clocks = <&rcc 1 CLK_USART3>;
288			status = "disabled";
289		};
290
291		usart4: serial@40004c00 {
292			compatible = "st,stm32f7-uart";
293			reg = <0x40004c00 0x400>;
294			interrupts = <52>;
295			clocks = <&rcc 1 CLK_UART4>;
296			status = "disabled";
297		};
298
299		usart5: serial@40005000 {
300			compatible = "st,stm32f7-uart";
301			reg = <0x40005000 0x400>;
302			interrupts = <53>;
303			clocks = <&rcc 1 CLK_UART5>;
304			status = "disabled";
305		};
306
307		i2c1: i2c@40005400 {
308			compatible = "st,stm32f7-i2c";
309			reg = <0x40005400 0x400>;
310			interrupts = <31>,
311				     <32>;
312			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
313			clocks = <&rcc 1 CLK_I2C1>;
314			#address-cells = <1>;
315			#size-cells = <0>;
316			i2c-analog-filter;
317			status = "disabled";
318		};
319
320		i2c2: i2c@40005800 {
321			compatible = "st,stm32f7-i2c";
322			reg = <0x40005800 0x400>;
323			interrupts = <33>,
324				     <34>;
325			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
326			clocks = <&rcc 1 CLK_I2C2>;
327			#address-cells = <1>;
328			#size-cells = <0>;
329			i2c-analog-filter;
330			status = "disabled";
331		};
332
333		i2c3: i2c@40005C00 {
334			compatible = "st,stm32f7-i2c";
335			reg = <0x40005C00 0x400>;
336			interrupts = <72>,
337				     <73>;
338			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
339			clocks = <&rcc 1 CLK_I2C3>;
340			#address-cells = <1>;
341			#size-cells = <0>;
342			i2c-analog-filter;
343			status = "disabled";
344		};
345
346		i2c4: i2c@40006000 {
347			compatible = "st,stm32f7-i2c";
348			reg = <0x40006000 0x400>;
349			interrupts = <95>,
350				     <96>;
351			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
352			clocks = <&rcc 1 CLK_I2C4>;
353			#address-cells = <1>;
354			#size-cells = <0>;
355			i2c-analog-filter;
356			status = "disabled";
357		};
358
359		cec: cec@40006c00 {
360			compatible = "st,stm32-cec";
361			reg = <0x40006C00 0x400>;
362			interrupts = <94>;
363			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
364			clock-names = "cec", "hdmi-cec";
365			status = "disabled";
366		};
367
368		usart7: serial@40007800 {
369			compatible = "st,stm32f7-uart";
370			reg = <0x40007800 0x400>;
371			interrupts = <82>;
372			clocks = <&rcc 1 CLK_UART7>;
373			status = "disabled";
374		};
375
376		usart8: serial@40007c00 {
377			compatible = "st,stm32f7-uart";
378			reg = <0x40007c00 0x400>;
379			interrupts = <83>;
380			clocks = <&rcc 1 CLK_UART8>;
381			status = "disabled";
382		};
383
384		timers1: timers@40010000 {
385			#address-cells = <1>;
386			#size-cells = <0>;
387			compatible = "st,stm32-timers";
388			reg = <0x40010000 0x400>;
389			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
390			clock-names = "int";
391			status = "disabled";
392
393			pwm {
394				compatible = "st,stm32-pwm";
395				#pwm-cells = <3>;
396				status = "disabled";
397			};
398
399			timer@0 {
400				compatible = "st,stm32-timer-trigger";
401				reg = <0>;
402				status = "disabled";
403			};
404		};
405
406		timers8: timers@40010400 {
407			#address-cells = <1>;
408			#size-cells = <0>;
409			compatible = "st,stm32-timers";
410			reg = <0x40010400 0x400>;
411			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
412			clock-names = "int";
413			status = "disabled";
414
415			pwm {
416				compatible = "st,stm32-pwm";
417				#pwm-cells = <3>;
418				status = "disabled";
419			};
420
421			timer@7 {
422				compatible = "st,stm32-timer-trigger";
423				reg = <7>;
424				status = "disabled";
425			};
426		};
427
428		usart1: serial@40011000 {
429			compatible = "st,stm32f7-uart";
430			reg = <0x40011000 0x400>;
431			interrupts = <37>;
432			clocks = <&rcc 1 CLK_USART1>;
433			status = "disabled";
434		};
435
436		usart6: serial@40011400 {
437			compatible = "st,stm32f7-uart";
438			reg = <0x40011400 0x400>;
439			interrupts = <71>;
440			clocks = <&rcc 1 CLK_USART6>;
441			status = "disabled";
442		};
443
444		sdio2: sdio2@40011c00 {
445			compatible = "arm,pl180", "arm,primecell";
446			arm,primecell-periphid = <0x00880180>;
447			reg = <0x40011c00 0x400>;
448			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
449			clock-names = "apb_pclk";
450			interrupts = <103>;
451			max-frequency = <48000000>;
452			status = "disabled";
453		};
454
455		sdio1: sdio1@40012c00 {
456			compatible = "arm,pl180", "arm,primecell";
457			arm,primecell-periphid = <0x00880180>;
458			reg = <0x40012c00 0x400>;
459			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
460			clock-names = "apb_pclk";
461			interrupts = <49>;
462			max-frequency = <48000000>;
463			status = "disabled";
464		};
465
466		syscfg: syscon@40013800 {
467			compatible = "st,stm32-syscfg", "syscon";
468			reg = <0x40013800 0x400>;
469		};
470
471		exti: interrupt-controller@40013c00 {
472			compatible = "st,stm32-exti";
473			interrupt-controller;
474			#interrupt-cells = <2>;
475			reg = <0x40013C00 0x400>;
476			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
477		};
478
479		timers9: timers@40014000 {
480			#address-cells = <1>;
481			#size-cells = <0>;
482			compatible = "st,stm32-timers";
483			reg = <0x40014000 0x400>;
484			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
485			clock-names = "int";
486			status = "disabled";
487
488			pwm {
489				compatible = "st,stm32-pwm";
490				#pwm-cells = <3>;
491				status = "disabled";
492			};
493
494			timer@8 {
495				compatible = "st,stm32-timer-trigger";
496				reg = <8>;
497				status = "disabled";
498			};
499		};
500
501		timers10: timers@40014400 {
502			#address-cells = <1>;
503			#size-cells = <0>;
504			compatible = "st,stm32-timers";
505			reg = <0x40014400 0x400>;
506			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
507			clock-names = "int";
508			status = "disabled";
509
510			pwm {
511				compatible = "st,stm32-pwm";
512				#pwm-cells = <3>;
513				status = "disabled";
514			};
515		};
516
517		timers11: timers@40014800 {
518			#address-cells = <1>;
519			#size-cells = <0>;
520			compatible = "st,stm32-timers";
521			reg = <0x40014800 0x400>;
522			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
523			clock-names = "int";
524			status = "disabled";
525
526			pwm {
527				compatible = "st,stm32-pwm";
528				#pwm-cells = <3>;
529				status = "disabled";
530			};
531		};
532
533		pwrcfg: power-config@40007000 {
534			compatible = "st,stm32-power-config", "syscon";
535			reg = <0x40007000 0x400>;
536		};
537
538		crc: crc@40023000 {
539			compatible = "st,stm32f7-crc";
540			reg = <0x40023000 0x400>;
541			clocks = <&rcc 0 12>;
542			status = "disabled";
543		};
544
545		rcc: rcc@40023800 {
546			#reset-cells = <1>;
547			#clock-cells = <2>;
548			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
549			reg = <0x40023800 0x400>;
550			clocks = <&clk_hse>, <&clk_i2s_ckin>;
551			st,syscfg = <&pwrcfg>;
552			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
553			assigned-clock-rates = <1000000>;
554		};
555
556		dma1: dma-controller@40026000 {
557			compatible = "st,stm32-dma";
558			reg = <0x40026000 0x400>;
559			interrupts = <11>,
560				     <12>,
561				     <13>,
562				     <14>,
563				     <15>,
564				     <16>,
565				     <17>,
566				     <47>;
567			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
568			#dma-cells = <4>;
569			status = "disabled";
570		};
571
572		dma2: dma-controller@40026400 {
573			compatible = "st,stm32-dma";
574			reg = <0x40026400 0x400>;
575			interrupts = <56>,
576				     <57>,
577				     <58>,
578				     <59>,
579				     <60>,
580				     <68>,
581				     <69>,
582				     <70>;
583			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
584			#dma-cells = <4>;
585			st,mem2mem;
586			status = "disabled";
587		};
588
589		usbotg_hs: usb@40040000 {
590			compatible = "st,stm32f7-hsotg";
591			reg = <0x40040000 0x40000>;
592			interrupts = <77>;
593			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
594			clock-names = "otg";
595			g-rx-fifo-size = <256>;
596			g-np-tx-fifo-size = <32>;
597			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
598			status = "disabled";
599		};
600
601		usbotg_fs: usb@50000000 {
602			compatible = "st,stm32f4x9-fsotg";
603			reg = <0x50000000 0x40000>;
604			interrupts = <67>;
605			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
606			clock-names = "otg";
607			status = "disabled";
608		};
609	};
610};
611
612&systick {
613	clocks = <&rcc 1 0>;
614	status = "okay";
615};
616