1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			clock-frequency = <650000000>;
21			device_type = "cpu";
22			reg = <0>;
23			operating-points-v2 = <&cpu0_opp_table>;
24			nvmem-cells = <&part_number_otp>;
25			nvmem-cell-names = "part_number";
26		};
27	};
28
29	cpu0_opp_table: cpu0-opp-table {
30		compatible = "operating-points-v2";
31		opp-shared;
32		opp-650000000 {
33			opp-hz = /bits/ 64 <650000000>;
34			opp-microvolt = <1200000>;
35			opp-supported-hw = <0x1>;
36		};
37		opp-800000000 {
38			opp-hz = /bits/ 64 <800000000>;
39			opp-microvolt = <1350000>;
40			opp-supported-hw = <0x2>;
41		};
42	};
43
44	arm-pmu {
45		compatible = "arm,cortex-a7-pmu";
46		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
47		interrupt-affinity = <&cpu0>;
48		interrupt-parent = <&intc>;
49	};
50
51	psci {
52		compatible = "arm,psci-1.0";
53		method = "smc";
54	};
55
56	intc: interrupt-controller@a0021000 {
57		compatible = "arm,cortex-a7-gic";
58		#interrupt-cells = <3>;
59		interrupt-controller;
60		reg = <0xa0021000 0x1000>,
61		      <0xa0022000 0x2000>;
62	};
63
64	timer {
65		compatible = "arm,armv7-timer";
66		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
67			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
68			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
69			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
70		interrupt-parent = <&intc>;
71	};
72
73	clocks {
74		clk_hse: clk-hse {
75			#clock-cells = <0>;
76			compatible = "fixed-clock";
77			clock-frequency = <24000000>;
78		};
79
80		clk_hsi: clk-hsi {
81			#clock-cells = <0>;
82			compatible = "fixed-clock";
83			clock-frequency = <64000000>;
84		};
85
86		clk_lse: clk-lse {
87			#clock-cells = <0>;
88			compatible = "fixed-clock";
89			clock-frequency = <32768>;
90		};
91
92		clk_lsi: clk-lsi {
93			#clock-cells = <0>;
94			compatible = "fixed-clock";
95			clock-frequency = <32000>;
96		};
97
98		clk_csi: clk-csi {
99			#clock-cells = <0>;
100			compatible = "fixed-clock";
101			clock-frequency = <4000000>;
102		};
103	};
104
105	thermal-zones {
106		cpu_thermal: cpu-thermal {
107			polling-delay-passive = <0>;
108			polling-delay = <0>;
109			thermal-sensors = <&dts>;
110
111			trips {
112				cpu_alert1: cpu-alert1 {
113					temperature = <85000>;
114					hysteresis = <0>;
115					type = "passive";
116				};
117
118				cpu-crit {
119					temperature = <120000>;
120					hysteresis = <0>;
121					type = "critical";
122				};
123			};
124
125			cooling-maps {
126			};
127		};
128	};
129
130	booster: regulator-booster {
131		compatible = "st,stm32mp1-booster";
132		st,syscfg = <&syscfg>;
133		status = "disabled";
134	};
135
136	soc {
137		compatible = "simple-bus";
138		#address-cells = <1>;
139		#size-cells = <1>;
140		interrupt-parent = <&intc>;
141		ranges;
142
143		timers2: timer@40000000 {
144			#address-cells = <1>;
145			#size-cells = <0>;
146			compatible = "st,stm32-timers";
147			reg = <0x40000000 0x400>;
148			clocks = <&rcc TIM2_K>;
149			clock-names = "int";
150			dmas = <&dmamux1 18 0x400 0x1>,
151			       <&dmamux1 19 0x400 0x1>,
152			       <&dmamux1 20 0x400 0x1>,
153			       <&dmamux1 21 0x400 0x1>,
154			       <&dmamux1 22 0x400 0x1>;
155			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
156			status = "disabled";
157
158			pwm {
159				compatible = "st,stm32-pwm";
160				#pwm-cells = <3>;
161				status = "disabled";
162			};
163
164			timer@1 {
165				compatible = "st,stm32h7-timer-trigger";
166				reg = <1>;
167				status = "disabled";
168			};
169
170			counter {
171				compatible = "st,stm32-timer-counter";
172				status = "disabled";
173			};
174		};
175
176		timers3: timer@40001000 {
177			#address-cells = <1>;
178			#size-cells = <0>;
179			compatible = "st,stm32-timers";
180			reg = <0x40001000 0x400>;
181			clocks = <&rcc TIM3_K>;
182			clock-names = "int";
183			dmas = <&dmamux1 23 0x400 0x1>,
184			       <&dmamux1 24 0x400 0x1>,
185			       <&dmamux1 25 0x400 0x1>,
186			       <&dmamux1 26 0x400 0x1>,
187			       <&dmamux1 27 0x400 0x1>,
188			       <&dmamux1 28 0x400 0x1>;
189			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
190			status = "disabled";
191
192			pwm {
193				compatible = "st,stm32-pwm";
194				#pwm-cells = <3>;
195				status = "disabled";
196			};
197
198			timer@2 {
199				compatible = "st,stm32h7-timer-trigger";
200				reg = <2>;
201				status = "disabled";
202			};
203
204			counter {
205				compatible = "st,stm32-timer-counter";
206				status = "disabled";
207			};
208		};
209
210		timers4: timer@40002000 {
211			#address-cells = <1>;
212			#size-cells = <0>;
213			compatible = "st,stm32-timers";
214			reg = <0x40002000 0x400>;
215			clocks = <&rcc TIM4_K>;
216			clock-names = "int";
217			dmas = <&dmamux1 29 0x400 0x1>,
218			       <&dmamux1 30 0x400 0x1>,
219			       <&dmamux1 31 0x400 0x1>,
220			       <&dmamux1 32 0x400 0x1>;
221			dma-names = "ch1", "ch2", "ch3", "ch4";
222			status = "disabled";
223
224			pwm {
225				compatible = "st,stm32-pwm";
226				#pwm-cells = <3>;
227				status = "disabled";
228			};
229
230			timer@3 {
231				compatible = "st,stm32h7-timer-trigger";
232				reg = <3>;
233				status = "disabled";
234			};
235
236			counter {
237				compatible = "st,stm32-timer-counter";
238				status = "disabled";
239			};
240		};
241
242		timers5: timer@40003000 {
243			#address-cells = <1>;
244			#size-cells = <0>;
245			compatible = "st,stm32-timers";
246			reg = <0x40003000 0x400>;
247			clocks = <&rcc TIM5_K>;
248			clock-names = "int";
249			dmas = <&dmamux1 55 0x400 0x1>,
250			       <&dmamux1 56 0x400 0x1>,
251			       <&dmamux1 57 0x400 0x1>,
252			       <&dmamux1 58 0x400 0x1>,
253			       <&dmamux1 59 0x400 0x1>,
254			       <&dmamux1 60 0x400 0x1>;
255			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
256			status = "disabled";
257
258			pwm {
259				compatible = "st,stm32-pwm";
260				#pwm-cells = <3>;
261				status = "disabled";
262			};
263
264			timer@4 {
265				compatible = "st,stm32h7-timer-trigger";
266				reg = <4>;
267				status = "disabled";
268			};
269
270			counter {
271				compatible = "st,stm32-timer-counter";
272				status = "disabled";
273			};
274		};
275
276		timers6: timer@40004000 {
277			#address-cells = <1>;
278			#size-cells = <0>;
279			compatible = "st,stm32-timers";
280			reg = <0x40004000 0x400>;
281			clocks = <&rcc TIM6_K>;
282			clock-names = "int";
283			dmas = <&dmamux1 69 0x400 0x1>;
284			dma-names = "up";
285			status = "disabled";
286
287			timer@5 {
288				compatible = "st,stm32h7-timer-trigger";
289				reg = <5>;
290				status = "disabled";
291			};
292		};
293
294		timers7: timer@40005000 {
295			#address-cells = <1>;
296			#size-cells = <0>;
297			compatible = "st,stm32-timers";
298			reg = <0x40005000 0x400>;
299			clocks = <&rcc TIM7_K>;
300			clock-names = "int";
301			dmas = <&dmamux1 70 0x400 0x1>;
302			dma-names = "up";
303			status = "disabled";
304
305			timer@6 {
306				compatible = "st,stm32h7-timer-trigger";
307				reg = <6>;
308				status = "disabled";
309			};
310		};
311
312		timers12: timer@40006000 {
313			#address-cells = <1>;
314			#size-cells = <0>;
315			compatible = "st,stm32-timers";
316			reg = <0x40006000 0x400>;
317			clocks = <&rcc TIM12_K>;
318			clock-names = "int";
319			status = "disabled";
320
321			pwm {
322				compatible = "st,stm32-pwm";
323				#pwm-cells = <3>;
324				status = "disabled";
325			};
326
327			timer@11 {
328				compatible = "st,stm32h7-timer-trigger";
329				reg = <11>;
330				status = "disabled";
331			};
332		};
333
334		timers13: timer@40007000 {
335			#address-cells = <1>;
336			#size-cells = <0>;
337			compatible = "st,stm32-timers";
338			reg = <0x40007000 0x400>;
339			clocks = <&rcc TIM13_K>;
340			clock-names = "int";
341			status = "disabled";
342
343			pwm {
344				compatible = "st,stm32-pwm";
345				#pwm-cells = <3>;
346				status = "disabled";
347			};
348
349			timer@12 {
350				compatible = "st,stm32h7-timer-trigger";
351				reg = <12>;
352				status = "disabled";
353			};
354		};
355
356		timers14: timer@40008000 {
357			#address-cells = <1>;
358			#size-cells = <0>;
359			compatible = "st,stm32-timers";
360			reg = <0x40008000 0x400>;
361			clocks = <&rcc TIM14_K>;
362			clock-names = "int";
363			status = "disabled";
364
365			pwm {
366				compatible = "st,stm32-pwm";
367				#pwm-cells = <3>;
368				status = "disabled";
369			};
370
371			timer@13 {
372				compatible = "st,stm32h7-timer-trigger";
373				reg = <13>;
374				status = "disabled";
375			};
376		};
377
378		lptimer1: timer@40009000 {
379			#address-cells = <1>;
380			#size-cells = <0>;
381			compatible = "st,stm32-lptimer";
382			reg = <0x40009000 0x400>;
383			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
384			clocks = <&rcc LPTIM1_K>;
385			clock-names = "mux";
386			wakeup-source;
387			status = "disabled";
388
389			pwm {
390				compatible = "st,stm32-pwm-lp";
391				#pwm-cells = <3>;
392				status = "disabled";
393			};
394
395			trigger@0 {
396				compatible = "st,stm32-lptimer-trigger";
397				reg = <0>;
398				status = "disabled";
399			};
400
401			counter {
402				compatible = "st,stm32-lptimer-counter";
403				status = "disabled";
404			};
405		};
406
407		spi2: spi@4000b000 {
408			#address-cells = <1>;
409			#size-cells = <0>;
410			compatible = "st,stm32h7-spi";
411			reg = <0x4000b000 0x400>;
412			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413			clocks = <&rcc SPI2_K>;
414			resets = <&rcc SPI2_R>;
415			dmas = <&dmamux1 39 0x400 0x05>,
416			       <&dmamux1 40 0x400 0x05>;
417			dma-names = "rx", "tx";
418			status = "disabled";
419		};
420
421		i2s2: audio-controller@4000b000 {
422			compatible = "st,stm32h7-i2s";
423			#sound-dai-cells = <0>;
424			reg = <0x4000b000 0x400>;
425			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
426			dmas = <&dmamux1 39 0x400 0x01>,
427			       <&dmamux1 40 0x400 0x01>;
428			dma-names = "rx", "tx";
429			status = "disabled";
430		};
431
432		spi3: spi@4000c000 {
433			#address-cells = <1>;
434			#size-cells = <0>;
435			compatible = "st,stm32h7-spi";
436			reg = <0x4000c000 0x400>;
437			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
438			clocks = <&rcc SPI3_K>;
439			resets = <&rcc SPI3_R>;
440			dmas = <&dmamux1 61 0x400 0x05>,
441			       <&dmamux1 62 0x400 0x05>;
442			dma-names = "rx", "tx";
443			status = "disabled";
444		};
445
446		i2s3: audio-controller@4000c000 {
447			compatible = "st,stm32h7-i2s";
448			#sound-dai-cells = <0>;
449			reg = <0x4000c000 0x400>;
450			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
451			dmas = <&dmamux1 61 0x400 0x01>,
452			       <&dmamux1 62 0x400 0x01>;
453			dma-names = "rx", "tx";
454			status = "disabled";
455		};
456
457		spdifrx: audio-controller@4000d000 {
458			compatible = "st,stm32h7-spdifrx";
459			#sound-dai-cells = <0>;
460			reg = <0x4000d000 0x400>;
461			clocks = <&rcc SPDIF_K>;
462			clock-names = "kclk";
463			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
464			dmas = <&dmamux1 93 0x400 0x01>,
465			       <&dmamux1 94 0x400 0x01>;
466			dma-names = "rx", "rx-ctrl";
467			status = "disabled";
468		};
469
470		usart2: serial@4000e000 {
471			compatible = "st,stm32h7-uart";
472			reg = <0x4000e000 0x400>;
473			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
474			clocks = <&rcc USART2_K>;
475			wakeup-source;
476			status = "disabled";
477		};
478
479		usart3: serial@4000f000 {
480			compatible = "st,stm32h7-uart";
481			reg = <0x4000f000 0x400>;
482			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
483			clocks = <&rcc USART3_K>;
484			wakeup-source;
485			status = "disabled";
486		};
487
488		uart4: serial@40010000 {
489			compatible = "st,stm32h7-uart";
490			reg = <0x40010000 0x400>;
491			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
492			clocks = <&rcc UART4_K>;
493			wakeup-source;
494			status = "disabled";
495		};
496
497		uart5: serial@40011000 {
498			compatible = "st,stm32h7-uart";
499			reg = <0x40011000 0x400>;
500			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&rcc UART5_K>;
502			wakeup-source;
503			status = "disabled";
504		};
505
506		i2c1: i2c@40012000 {
507			compatible = "st,stm32mp15-i2c";
508			reg = <0x40012000 0x400>;
509			interrupt-names = "event", "error";
510			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
511				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
512			clocks = <&rcc I2C1_K>;
513			resets = <&rcc I2C1_R>;
514			#address-cells = <1>;
515			#size-cells = <0>;
516			st,syscfg-fmp = <&syscfg 0x4 0x1>;
517			wakeup-source;
518			i2c-analog-filter;
519			status = "disabled";
520		};
521
522		i2c2: i2c@40013000 {
523			compatible = "st,stm32mp15-i2c";
524			reg = <0x40013000 0x400>;
525			interrupt-names = "event", "error";
526			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
527				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
528			clocks = <&rcc I2C2_K>;
529			resets = <&rcc I2C2_R>;
530			#address-cells = <1>;
531			#size-cells = <0>;
532			st,syscfg-fmp = <&syscfg 0x4 0x2>;
533			wakeup-source;
534			i2c-analog-filter;
535			status = "disabled";
536		};
537
538		i2c3: i2c@40014000 {
539			compatible = "st,stm32mp15-i2c";
540			reg = <0x40014000 0x400>;
541			interrupt-names = "event", "error";
542			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
543				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
544			clocks = <&rcc I2C3_K>;
545			resets = <&rcc I2C3_R>;
546			#address-cells = <1>;
547			#size-cells = <0>;
548			st,syscfg-fmp = <&syscfg 0x4 0x4>;
549			wakeup-source;
550			i2c-analog-filter;
551			status = "disabled";
552		};
553
554		i2c5: i2c@40015000 {
555			compatible = "st,stm32mp15-i2c";
556			reg = <0x40015000 0x400>;
557			interrupt-names = "event", "error";
558			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
559				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
560			clocks = <&rcc I2C5_K>;
561			resets = <&rcc I2C5_R>;
562			#address-cells = <1>;
563			#size-cells = <0>;
564			st,syscfg-fmp = <&syscfg 0x4 0x10>;
565			wakeup-source;
566			i2c-analog-filter;
567			status = "disabled";
568		};
569
570		cec: cec@40016000 {
571			compatible = "st,stm32-cec";
572			reg = <0x40016000 0x400>;
573			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
574			clocks = <&rcc CEC_K>, <&clk_lse>;
575			clock-names = "cec", "hdmi-cec";
576			status = "disabled";
577		};
578
579		dac: dac@40017000 {
580			compatible = "st,stm32h7-dac-core";
581			reg = <0x40017000 0x400>;
582			clocks = <&rcc DAC12>;
583			clock-names = "pclk";
584			#address-cells = <1>;
585			#size-cells = <0>;
586			status = "disabled";
587
588			dac1: dac@1 {
589				compatible = "st,stm32-dac";
590				#io-channel-cells = <1>;
591				reg = <1>;
592				status = "disabled";
593			};
594
595			dac2: dac@2 {
596				compatible = "st,stm32-dac";
597				#io-channel-cells = <1>;
598				reg = <2>;
599				status = "disabled";
600			};
601		};
602
603		uart7: serial@40018000 {
604			compatible = "st,stm32h7-uart";
605			reg = <0x40018000 0x400>;
606			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
607			clocks = <&rcc UART7_K>;
608			wakeup-source;
609			status = "disabled";
610		};
611
612		uart8: serial@40019000 {
613			compatible = "st,stm32h7-uart";
614			reg = <0x40019000 0x400>;
615			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
616			clocks = <&rcc UART8_K>;
617			wakeup-source;
618			status = "disabled";
619		};
620
621		timers1: timer@44000000 {
622			#address-cells = <1>;
623			#size-cells = <0>;
624			compatible = "st,stm32-timers";
625			reg = <0x44000000 0x400>;
626			clocks = <&rcc TIM1_K>;
627			clock-names = "int";
628			dmas = <&dmamux1 11 0x400 0x1>,
629			       <&dmamux1 12 0x400 0x1>,
630			       <&dmamux1 13 0x400 0x1>,
631			       <&dmamux1 14 0x400 0x1>,
632			       <&dmamux1 15 0x400 0x1>,
633			       <&dmamux1 16 0x400 0x1>,
634			       <&dmamux1 17 0x400 0x1>;
635			dma-names = "ch1", "ch2", "ch3", "ch4",
636				    "up", "trig", "com";
637			status = "disabled";
638
639			pwm {
640				compatible = "st,stm32-pwm";
641				#pwm-cells = <3>;
642				status = "disabled";
643			};
644
645			timer@0 {
646				compatible = "st,stm32h7-timer-trigger";
647				reg = <0>;
648				status = "disabled";
649			};
650
651			counter {
652				compatible = "st,stm32-timer-counter";
653				status = "disabled";
654			};
655		};
656
657		timers8: timer@44001000 {
658			#address-cells = <1>;
659			#size-cells = <0>;
660			compatible = "st,stm32-timers";
661			reg = <0x44001000 0x400>;
662			clocks = <&rcc TIM8_K>;
663			clock-names = "int";
664			dmas = <&dmamux1 47 0x400 0x1>,
665			       <&dmamux1 48 0x400 0x1>,
666			       <&dmamux1 49 0x400 0x1>,
667			       <&dmamux1 50 0x400 0x1>,
668			       <&dmamux1 51 0x400 0x1>,
669			       <&dmamux1 52 0x400 0x1>,
670			       <&dmamux1 53 0x400 0x1>;
671			dma-names = "ch1", "ch2", "ch3", "ch4",
672				    "up", "trig", "com";
673			status = "disabled";
674
675			pwm {
676				compatible = "st,stm32-pwm";
677				#pwm-cells = <3>;
678				status = "disabled";
679			};
680
681			timer@7 {
682				compatible = "st,stm32h7-timer-trigger";
683				reg = <7>;
684				status = "disabled";
685			};
686
687			counter {
688				compatible = "st,stm32-timer-counter";
689				status = "disabled";
690			};
691		};
692
693		usart6: serial@44003000 {
694			compatible = "st,stm32h7-uart";
695			reg = <0x44003000 0x400>;
696			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
697			clocks = <&rcc USART6_K>;
698			wakeup-source;
699			status = "disabled";
700		};
701
702		spi1: spi@44004000 {
703			#address-cells = <1>;
704			#size-cells = <0>;
705			compatible = "st,stm32h7-spi";
706			reg = <0x44004000 0x400>;
707			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
708			clocks = <&rcc SPI1_K>;
709			resets = <&rcc SPI1_R>;
710			dmas = <&dmamux1 37 0x400 0x05>,
711			       <&dmamux1 38 0x400 0x05>;
712			dma-names = "rx", "tx";
713			status = "disabled";
714		};
715
716		i2s1: audio-controller@44004000 {
717			compatible = "st,stm32h7-i2s";
718			#sound-dai-cells = <0>;
719			reg = <0x44004000 0x400>;
720			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
721			dmas = <&dmamux1 37 0x400 0x01>,
722			       <&dmamux1 38 0x400 0x01>;
723			dma-names = "rx", "tx";
724			status = "disabled";
725		};
726
727		spi4: spi@44005000 {
728			#address-cells = <1>;
729			#size-cells = <0>;
730			compatible = "st,stm32h7-spi";
731			reg = <0x44005000 0x400>;
732			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
733			clocks = <&rcc SPI4_K>;
734			resets = <&rcc SPI4_R>;
735			dmas = <&dmamux1 83 0x400 0x05>,
736			       <&dmamux1 84 0x400 0x05>;
737			dma-names = "rx", "tx";
738			status = "disabled";
739		};
740
741		timers15: timer@44006000 {
742			#address-cells = <1>;
743			#size-cells = <0>;
744			compatible = "st,stm32-timers";
745			reg = <0x44006000 0x400>;
746			clocks = <&rcc TIM15_K>;
747			clock-names = "int";
748			dmas = <&dmamux1 105 0x400 0x1>,
749			       <&dmamux1 106 0x400 0x1>,
750			       <&dmamux1 107 0x400 0x1>,
751			       <&dmamux1 108 0x400 0x1>;
752			dma-names = "ch1", "up", "trig", "com";
753			status = "disabled";
754
755			pwm {
756				compatible = "st,stm32-pwm";
757				#pwm-cells = <3>;
758				status = "disabled";
759			};
760
761			timer@14 {
762				compatible = "st,stm32h7-timer-trigger";
763				reg = <14>;
764				status = "disabled";
765			};
766		};
767
768		timers16: timer@44007000 {
769			#address-cells = <1>;
770			#size-cells = <0>;
771			compatible = "st,stm32-timers";
772			reg = <0x44007000 0x400>;
773			clocks = <&rcc TIM16_K>;
774			clock-names = "int";
775			dmas = <&dmamux1 109 0x400 0x1>,
776			       <&dmamux1 110 0x400 0x1>;
777			dma-names = "ch1", "up";
778			status = "disabled";
779
780			pwm {
781				compatible = "st,stm32-pwm";
782				#pwm-cells = <3>;
783				status = "disabled";
784			};
785			timer@15 {
786				compatible = "st,stm32h7-timer-trigger";
787				reg = <15>;
788				status = "disabled";
789			};
790		};
791
792		timers17: timer@44008000 {
793			#address-cells = <1>;
794			#size-cells = <0>;
795			compatible = "st,stm32-timers";
796			reg = <0x44008000 0x400>;
797			clocks = <&rcc TIM17_K>;
798			clock-names = "int";
799			dmas = <&dmamux1 111 0x400 0x1>,
800			       <&dmamux1 112 0x400 0x1>;
801			dma-names = "ch1", "up";
802			status = "disabled";
803
804			pwm {
805				compatible = "st,stm32-pwm";
806				#pwm-cells = <3>;
807				status = "disabled";
808			};
809
810			timer@16 {
811				compatible = "st,stm32h7-timer-trigger";
812				reg = <16>;
813				status = "disabled";
814			};
815		};
816
817		spi5: spi@44009000 {
818			#address-cells = <1>;
819			#size-cells = <0>;
820			compatible = "st,stm32h7-spi";
821			reg = <0x44009000 0x400>;
822			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
823			clocks = <&rcc SPI5_K>;
824			resets = <&rcc SPI5_R>;
825			dmas = <&dmamux1 85 0x400 0x05>,
826			       <&dmamux1 86 0x400 0x05>;
827			dma-names = "rx", "tx";
828			status = "disabled";
829		};
830
831		sai1: sai@4400a000 {
832			compatible = "st,stm32h7-sai";
833			#address-cells = <1>;
834			#size-cells = <1>;
835			ranges = <0 0x4400a000 0x400>;
836			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
837			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
838			resets = <&rcc SAI1_R>;
839			status = "disabled";
840
841			sai1a: audio-controller@4400a004 {
842				#sound-dai-cells = <0>;
843
844				compatible = "st,stm32-sai-sub-a";
845				reg = <0x4 0x1c>;
846				clocks = <&rcc SAI1_K>;
847				clock-names = "sai_ck";
848				dmas = <&dmamux1 87 0x400 0x01>;
849				status = "disabled";
850			};
851
852			sai1b: audio-controller@4400a024 {
853				#sound-dai-cells = <0>;
854				compatible = "st,stm32-sai-sub-b";
855				reg = <0x24 0x1c>;
856				clocks = <&rcc SAI1_K>;
857				clock-names = "sai_ck";
858				dmas = <&dmamux1 88 0x400 0x01>;
859				status = "disabled";
860			};
861		};
862
863		sai2: sai@4400b000 {
864			compatible = "st,stm32h7-sai";
865			#address-cells = <1>;
866			#size-cells = <1>;
867			ranges = <0 0x4400b000 0x400>;
868			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
869			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
870			resets = <&rcc SAI2_R>;
871			status = "disabled";
872
873			sai2a: audio-controller@4400b004 {
874				#sound-dai-cells = <0>;
875				compatible = "st,stm32-sai-sub-a";
876				reg = <0x4 0x1c>;
877				clocks = <&rcc SAI2_K>;
878				clock-names = "sai_ck";
879				dmas = <&dmamux1 89 0x400 0x01>;
880				status = "disabled";
881			};
882
883			sai2b: audio-controller@4400b024 {
884				#sound-dai-cells = <0>;
885				compatible = "st,stm32-sai-sub-b";
886				reg = <0x24 0x1c>;
887				clocks = <&rcc SAI2_K>;
888				clock-names = "sai_ck";
889				dmas = <&dmamux1 90 0x400 0x01>;
890				status = "disabled";
891			};
892		};
893
894		sai3: sai@4400c000 {
895			compatible = "st,stm32h7-sai";
896			#address-cells = <1>;
897			#size-cells = <1>;
898			ranges = <0 0x4400c000 0x400>;
899			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
900			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
901			resets = <&rcc SAI3_R>;
902			status = "disabled";
903
904			sai3a: audio-controller@4400c004 {
905				#sound-dai-cells = <0>;
906				compatible = "st,stm32-sai-sub-a";
907				reg = <0x04 0x1c>;
908				clocks = <&rcc SAI3_K>;
909				clock-names = "sai_ck";
910				dmas = <&dmamux1 113 0x400 0x01>;
911				status = "disabled";
912			};
913
914			sai3b: audio-controller@4400c024 {
915				#sound-dai-cells = <0>;
916				compatible = "st,stm32-sai-sub-b";
917				reg = <0x24 0x1c>;
918				clocks = <&rcc SAI3_K>;
919				clock-names = "sai_ck";
920				dmas = <&dmamux1 114 0x400 0x01>;
921				status = "disabled";
922			};
923		};
924
925		dfsdm: dfsdm@4400d000 {
926			compatible = "st,stm32mp1-dfsdm";
927			reg = <0x4400d000 0x800>;
928			clocks = <&rcc DFSDM_K>;
929			clock-names = "dfsdm";
930			#address-cells = <1>;
931			#size-cells = <0>;
932			status = "disabled";
933
934			dfsdm0: filter@0 {
935				compatible = "st,stm32-dfsdm-adc";
936				#io-channel-cells = <1>;
937				reg = <0>;
938				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
939				dmas = <&dmamux1 101 0x400 0x01>;
940				dma-names = "rx";
941				status = "disabled";
942			};
943
944			dfsdm1: filter@1 {
945				compatible = "st,stm32-dfsdm-adc";
946				#io-channel-cells = <1>;
947				reg = <1>;
948				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
949				dmas = <&dmamux1 102 0x400 0x01>;
950				dma-names = "rx";
951				status = "disabled";
952			};
953
954			dfsdm2: filter@2 {
955				compatible = "st,stm32-dfsdm-adc";
956				#io-channel-cells = <1>;
957				reg = <2>;
958				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
959				dmas = <&dmamux1 103 0x400 0x01>;
960				dma-names = "rx";
961				status = "disabled";
962			};
963
964			dfsdm3: filter@3 {
965				compatible = "st,stm32-dfsdm-adc";
966				#io-channel-cells = <1>;
967				reg = <3>;
968				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
969				dmas = <&dmamux1 104 0x400 0x01>;
970				dma-names = "rx";
971				status = "disabled";
972			};
973
974			dfsdm4: filter@4 {
975				compatible = "st,stm32-dfsdm-adc";
976				#io-channel-cells = <1>;
977				reg = <4>;
978				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
979				dmas = <&dmamux1 91 0x400 0x01>;
980				dma-names = "rx";
981				status = "disabled";
982			};
983
984			dfsdm5: filter@5 {
985				compatible = "st,stm32-dfsdm-adc";
986				#io-channel-cells = <1>;
987				reg = <5>;
988				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
989				dmas = <&dmamux1 92 0x400 0x01>;
990				dma-names = "rx";
991				status = "disabled";
992			};
993		};
994
995		dma1: dma-controller@48000000 {
996			compatible = "st,stm32-dma";
997			reg = <0x48000000 0x400>;
998			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
999				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1000				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1001				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1002				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1003				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1004				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1005				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1006			clocks = <&rcc DMA1>;
1007			resets = <&rcc DMA1_R>;
1008			#dma-cells = <4>;
1009			st,mem2mem;
1010			dma-requests = <8>;
1011		};
1012
1013		dma2: dma-controller@48001000 {
1014			compatible = "st,stm32-dma";
1015			reg = <0x48001000 0x400>;
1016			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1017				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1018				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1019				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1020				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1021				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1022				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1023				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1024			clocks = <&rcc DMA2>;
1025			resets = <&rcc DMA2_R>;
1026			#dma-cells = <4>;
1027			st,mem2mem;
1028			dma-requests = <8>;
1029		};
1030
1031		dmamux1: dma-router@48002000 {
1032			compatible = "st,stm32h7-dmamux";
1033			reg = <0x48002000 0x40>;
1034			#dma-cells = <3>;
1035			dma-requests = <128>;
1036			dma-masters = <&dma1 &dma2>;
1037			dma-channels = <16>;
1038			clocks = <&rcc DMAMUX>;
1039			resets = <&rcc DMAMUX_R>;
1040		};
1041
1042		adc: adc@48003000 {
1043			compatible = "st,stm32mp1-adc-core";
1044			reg = <0x48003000 0x400>;
1045			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1046				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1047			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1048			clock-names = "bus", "adc";
1049			interrupt-controller;
1050			st,syscfg = <&syscfg>;
1051			#interrupt-cells = <1>;
1052			#address-cells = <1>;
1053			#size-cells = <0>;
1054			status = "disabled";
1055
1056			adc1: adc@0 {
1057				compatible = "st,stm32mp1-adc";
1058				#io-channel-cells = <1>;
1059				reg = <0x0>;
1060				interrupt-parent = <&adc>;
1061				interrupts = <0>;
1062				dmas = <&dmamux1 9 0x400 0x01>;
1063				dma-names = "rx";
1064				status = "disabled";
1065			};
1066
1067			adc2: adc@100 {
1068				compatible = "st,stm32mp1-adc";
1069				#io-channel-cells = <1>;
1070				reg = <0x100>;
1071				interrupt-parent = <&adc>;
1072				interrupts = <1>;
1073				dmas = <&dmamux1 10 0x400 0x01>;
1074				dma-names = "rx";
1075				status = "disabled";
1076			};
1077		};
1078
1079		sdmmc3: mmc@48004000 {
1080			compatible = "arm,pl18x", "arm,primecell";
1081			arm,primecell-periphid = <0x00253180>;
1082			reg = <0x48004000 0x400>;
1083			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1084			interrupt-names = "cmd_irq";
1085			clocks = <&rcc SDMMC3_K>;
1086			clock-names = "apb_pclk";
1087			resets = <&rcc SDMMC3_R>;
1088			cap-sd-highspeed;
1089			cap-mmc-highspeed;
1090			max-frequency = <120000000>;
1091			status = "disabled";
1092		};
1093
1094		usbotg_hs: usb-otg@49000000 {
1095			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1096			reg = <0x49000000 0x10000>;
1097			clocks = <&rcc USBO_K>;
1098			clock-names = "otg";
1099			resets = <&rcc USBO_R>;
1100			reset-names = "dwc2";
1101			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1102			g-rx-fifo-size = <512>;
1103			g-np-tx-fifo-size = <32>;
1104			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1105			dr_mode = "otg";
1106			usb33d-supply = <&usb33>;
1107			status = "disabled";
1108		};
1109
1110		hwspinlock: hwspinlock@4c000000 {
1111			compatible = "st,stm32-hwspinlock";
1112			#hwlock-cells = <1>;
1113			reg = <0x4c000000 0x400>;
1114			clocks = <&rcc HSEM>;
1115			clock-names = "hwspinlock";
1116		};
1117
1118		ipcc: mailbox@4c001000 {
1119			compatible = "st,stm32mp1-ipcc";
1120			#mbox-cells = <1>;
1121			reg = <0x4c001000 0x400>;
1122			st,proc-id = <0>;
1123			interrupts-extended =
1124				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1125				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1126				<&exti 61 1>;
1127			interrupt-names = "rx", "tx", "wakeup";
1128			clocks = <&rcc IPCC>;
1129			wakeup-source;
1130			status = "disabled";
1131		};
1132
1133		dcmi: dcmi@4c006000 {
1134			compatible = "st,stm32-dcmi";
1135			reg = <0x4c006000 0x400>;
1136			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1137			resets = <&rcc CAMITF_R>;
1138			clocks = <&rcc DCMI>;
1139			clock-names = "mclk";
1140			dmas = <&dmamux1 75 0x400 0x01>;
1141			dma-names = "tx";
1142			status = "disabled";
1143		};
1144
1145		rcc: rcc@50000000 {
1146			compatible = "st,stm32mp1-rcc", "syscon";
1147			reg = <0x50000000 0x1000>;
1148			#clock-cells = <1>;
1149			#reset-cells = <1>;
1150
1151			clock-names = "hse", "hsi", "csi", "lse", "lsi";
1152			clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
1153				 <&clk_lse>, <&clk_lsi>;
1154		};
1155
1156		pwr_regulators: pwr@50001000 {
1157			compatible = "st,stm32mp1,pwr-reg";
1158			reg = <0x50001000 0x10>;
1159
1160			reg11: reg11 {
1161				regulator-name = "reg11";
1162				regulator-min-microvolt = <1100000>;
1163				regulator-max-microvolt = <1100000>;
1164			};
1165
1166			reg18: reg18 {
1167				regulator-name = "reg18";
1168				regulator-min-microvolt = <1800000>;
1169				regulator-max-microvolt = <1800000>;
1170			};
1171
1172			usb33: usb33 {
1173				regulator-name = "usb33";
1174				regulator-min-microvolt = <3300000>;
1175				regulator-max-microvolt = <3300000>;
1176			};
1177		};
1178
1179		pwr_mcu: pwr_mcu@50001014 {
1180			compatible = "st,stm32mp151-pwr-mcu", "syscon";
1181			reg = <0x50001014 0x4>;
1182		};
1183
1184		exti: interrupt-controller@5000d000 {
1185			compatible = "st,stm32mp1-exti", "syscon";
1186			interrupt-controller;
1187			#interrupt-cells = <2>;
1188			reg = <0x5000d000 0x400>;
1189		};
1190
1191		syscfg: syscon@50020000 {
1192			compatible = "st,stm32mp157-syscfg", "syscon";
1193			reg = <0x50020000 0x400>;
1194			clocks = <&rcc SYSCFG>;
1195		};
1196
1197		lptimer2: timer@50021000 {
1198			#address-cells = <1>;
1199			#size-cells = <0>;
1200			compatible = "st,stm32-lptimer";
1201			reg = <0x50021000 0x400>;
1202			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1203			clocks = <&rcc LPTIM2_K>;
1204			clock-names = "mux";
1205			wakeup-source;
1206			status = "disabled";
1207
1208			pwm {
1209				compatible = "st,stm32-pwm-lp";
1210				#pwm-cells = <3>;
1211				status = "disabled";
1212			};
1213
1214			trigger@1 {
1215				compatible = "st,stm32-lptimer-trigger";
1216				reg = <1>;
1217				status = "disabled";
1218			};
1219
1220			counter {
1221				compatible = "st,stm32-lptimer-counter";
1222				status = "disabled";
1223			};
1224		};
1225
1226		lptimer3: timer@50022000 {
1227			#address-cells = <1>;
1228			#size-cells = <0>;
1229			compatible = "st,stm32-lptimer";
1230			reg = <0x50022000 0x400>;
1231			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1232			clocks = <&rcc LPTIM3_K>;
1233			clock-names = "mux";
1234			wakeup-source;
1235			status = "disabled";
1236
1237			pwm {
1238				compatible = "st,stm32-pwm-lp";
1239				#pwm-cells = <3>;
1240				status = "disabled";
1241			};
1242
1243			trigger@2 {
1244				compatible = "st,stm32-lptimer-trigger";
1245				reg = <2>;
1246				status = "disabled";
1247			};
1248		};
1249
1250		lptimer4: timer@50023000 {
1251			compatible = "st,stm32-lptimer";
1252			reg = <0x50023000 0x400>;
1253			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1254			clocks = <&rcc LPTIM4_K>;
1255			clock-names = "mux";
1256			wakeup-source;
1257			status = "disabled";
1258
1259			pwm {
1260				compatible = "st,stm32-pwm-lp";
1261				#pwm-cells = <3>;
1262				status = "disabled";
1263			};
1264		};
1265
1266		lptimer5: timer@50024000 {
1267			compatible = "st,stm32-lptimer";
1268			reg = <0x50024000 0x400>;
1269			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1270			clocks = <&rcc LPTIM5_K>;
1271			clock-names = "mux";
1272			wakeup-source;
1273			status = "disabled";
1274
1275			pwm {
1276				compatible = "st,stm32-pwm-lp";
1277				#pwm-cells = <3>;
1278				status = "disabled";
1279			};
1280		};
1281
1282		vrefbuf: vrefbuf@50025000 {
1283			compatible = "st,stm32-vrefbuf";
1284			reg = <0x50025000 0x8>;
1285			regulator-min-microvolt = <1500000>;
1286			regulator-max-microvolt = <2500000>;
1287			clocks = <&rcc VREF>;
1288			status = "disabled";
1289		};
1290
1291		sai4: sai@50027000 {
1292			compatible = "st,stm32h7-sai";
1293			#address-cells = <1>;
1294			#size-cells = <1>;
1295			ranges = <0 0x50027000 0x400>;
1296			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1297			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1298			resets = <&rcc SAI4_R>;
1299			status = "disabled";
1300
1301			sai4a: audio-controller@50027004 {
1302				#sound-dai-cells = <0>;
1303				compatible = "st,stm32-sai-sub-a";
1304				reg = <0x04 0x1c>;
1305				clocks = <&rcc SAI4_K>;
1306				clock-names = "sai_ck";
1307				dmas = <&dmamux1 99 0x400 0x01>;
1308				status = "disabled";
1309			};
1310
1311			sai4b: audio-controller@50027024 {
1312				#sound-dai-cells = <0>;
1313				compatible = "st,stm32-sai-sub-b";
1314				reg = <0x24 0x1c>;
1315				clocks = <&rcc SAI4_K>;
1316				clock-names = "sai_ck";
1317				dmas = <&dmamux1 100 0x400 0x01>;
1318				status = "disabled";
1319			};
1320		};
1321
1322		dts: thermal@50028000 {
1323			compatible = "st,stm32-thermal";
1324			reg = <0x50028000 0x100>;
1325			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1326			clocks = <&rcc TMPSENS>;
1327			clock-names = "pclk";
1328			#thermal-sensor-cells = <0>;
1329			status = "disabled";
1330		};
1331
1332		hash1: hash@54002000 {
1333			compatible = "st,stm32f756-hash";
1334			reg = <0x54002000 0x400>;
1335			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1336			clocks = <&rcc HASH1>;
1337			resets = <&rcc HASH1_R>;
1338			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1339			dma-names = "in";
1340			dma-maxburst = <2>;
1341			status = "disabled";
1342		};
1343
1344		rng1: rng@54003000 {
1345			compatible = "st,stm32-rng";
1346			reg = <0x54003000 0x400>;
1347			clocks = <&rcc RNG1_K>;
1348			resets = <&rcc RNG1_R>;
1349			status = "disabled";
1350		};
1351
1352		mdma1: dma-controller@58000000 {
1353			compatible = "st,stm32h7-mdma";
1354			reg = <0x58000000 0x1000>;
1355			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1356			clocks = <&rcc MDMA>;
1357			resets = <&rcc MDMA_R>;
1358			#dma-cells = <5>;
1359			dma-channels = <32>;
1360			dma-requests = <48>;
1361		};
1362
1363		fmc: memory-controller@58002000 {
1364			#address-cells = <2>;
1365			#size-cells = <1>;
1366			compatible = "st,stm32mp1-fmc2-ebi";
1367			reg = <0x58002000 0x1000>;
1368			clocks = <&rcc FMC_K>;
1369			resets = <&rcc FMC_R>;
1370			status = "disabled";
1371
1372			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1373				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1374				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1375				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1376				 <4 0 0x80000000 0x10000000>; /* NAND */
1377
1378			nand-controller@4,0 {
1379				#address-cells = <1>;
1380				#size-cells = <0>;
1381				compatible = "st,stm32mp1-fmc2-nfc";
1382				reg = <4 0x00000000 0x1000>,
1383				      <4 0x08010000 0x1000>,
1384				      <4 0x08020000 0x1000>,
1385				      <4 0x01000000 0x1000>,
1386				      <4 0x09010000 0x1000>,
1387				      <4 0x09020000 0x1000>;
1388				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1389				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1390				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1391				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1392				dma-names = "tx", "rx", "ecc";
1393				status = "disabled";
1394			};
1395		};
1396
1397		qspi: spi@58003000 {
1398			compatible = "st,stm32f469-qspi";
1399			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1400			reg-names = "qspi", "qspi_mm";
1401			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1402			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1403			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1404			dma-names = "tx", "rx";
1405			clocks = <&rcc QSPI_K>;
1406			resets = <&rcc QSPI_R>;
1407			#address-cells = <1>;
1408			#size-cells = <0>;
1409			status = "disabled";
1410		};
1411
1412		sdmmc1: mmc@58005000 {
1413			compatible = "arm,pl18x", "arm,primecell";
1414			arm,primecell-periphid = <0x00253180>;
1415			reg = <0x58005000 0x1000>;
1416			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1417			interrupt-names = "cmd_irq";
1418			clocks = <&rcc SDMMC1_K>;
1419			clock-names = "apb_pclk";
1420			resets = <&rcc SDMMC1_R>;
1421			cap-sd-highspeed;
1422			cap-mmc-highspeed;
1423			max-frequency = <120000000>;
1424			status = "disabled";
1425		};
1426
1427		sdmmc2: mmc@58007000 {
1428			compatible = "arm,pl18x", "arm,primecell";
1429			arm,primecell-periphid = <0x00253180>;
1430			reg = <0x58007000 0x1000>;
1431			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1432			interrupt-names = "cmd_irq";
1433			clocks = <&rcc SDMMC2_K>;
1434			clock-names = "apb_pclk";
1435			resets = <&rcc SDMMC2_R>;
1436			cap-sd-highspeed;
1437			cap-mmc-highspeed;
1438			max-frequency = <120000000>;
1439			status = "disabled";
1440		};
1441
1442		crc1: crc@58009000 {
1443			compatible = "st,stm32f7-crc";
1444			reg = <0x58009000 0x400>;
1445			clocks = <&rcc CRC1>;
1446			status = "disabled";
1447		};
1448
1449		ethernet0: ethernet@5800a000 {
1450			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1451			reg = <0x5800a000 0x2000>;
1452			reg-names = "stmmaceth";
1453			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1454			interrupt-names = "macirq";
1455			clock-names = "stmmaceth",
1456				      "mac-clk-tx",
1457				      "mac-clk-rx",
1458				      "eth-ck",
1459				      "ptp_ref",
1460				      "ethstp";
1461			clocks = <&rcc ETHMAC>,
1462				 <&rcc ETHTX>,
1463				 <&rcc ETHRX>,
1464				 <&rcc ETHCK_K>,
1465				 <&rcc ETHPTP_K>,
1466				 <&rcc ETHSTP>;
1467			st,syscon = <&syscfg 0x4>;
1468			snps,mixed-burst;
1469			snps,pbl = <2>;
1470			snps,en-tx-lpi-clockgating;
1471			snps,axi-config = <&stmmac_axi_config_0>;
1472			snps,tso;
1473			status = "disabled";
1474
1475			stmmac_axi_config_0: stmmac-axi-config {
1476				snps,wr_osr_lmt = <0x7>;
1477				snps,rd_osr_lmt = <0x7>;
1478				snps,blen = <0 0 0 0 16 8 4>;
1479			};
1480		};
1481
1482		usbh_ohci: usb@5800c000 {
1483			compatible = "generic-ohci";
1484			reg = <0x5800c000 0x1000>;
1485			clocks = <&rcc USBH>;
1486			resets = <&rcc USBH_R>;
1487			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1488			status = "disabled";
1489		};
1490
1491		usbh_ehci: usb@5800d000 {
1492			compatible = "generic-ehci";
1493			reg = <0x5800d000 0x1000>;
1494			clocks = <&rcc USBH>;
1495			resets = <&rcc USBH_R>;
1496			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1497			companion = <&usbh_ohci>;
1498			status = "disabled";
1499		};
1500
1501		ltdc: display-controller@5a001000 {
1502			compatible = "st,stm32-ltdc";
1503			reg = <0x5a001000 0x400>;
1504			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1505				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1506			clocks = <&rcc LTDC_PX>;
1507			clock-names = "lcd";
1508			resets = <&rcc LTDC_R>;
1509			status = "disabled";
1510
1511			port {
1512				#address-cells = <1>;
1513				#size-cells = <0>;
1514			};
1515		};
1516
1517		iwdg2: watchdog@5a002000 {
1518			compatible = "st,stm32mp1-iwdg";
1519			reg = <0x5a002000 0x400>;
1520			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1521			clock-names = "pclk", "lsi";
1522			status = "disabled";
1523		};
1524
1525		usbphyc: usbphyc@5a006000 {
1526			#address-cells = <1>;
1527			#size-cells = <0>;
1528			#clock-cells = <0>;
1529			compatible = "st,stm32mp1-usbphyc";
1530			reg = <0x5a006000 0x1000>;
1531			clocks = <&rcc USBPHY_K>;
1532			resets = <&rcc USBPHY_R>;
1533			vdda1v1-supply = <&reg11>;
1534			vdda1v8-supply = <&reg18>;
1535			status = "disabled";
1536
1537			usbphyc_port0: usb-phy@0 {
1538				#phy-cells = <0>;
1539				reg = <0>;
1540			};
1541
1542			usbphyc_port1: usb-phy@1 {
1543				#phy-cells = <1>;
1544				reg = <1>;
1545			};
1546		};
1547
1548		usart1: serial@5c000000 {
1549			compatible = "st,stm32h7-uart";
1550			reg = <0x5c000000 0x400>;
1551			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1552			clocks = <&rcc USART1_K>;
1553			wakeup-source;
1554			status = "disabled";
1555		};
1556
1557		spi6: spi@5c001000 {
1558			#address-cells = <1>;
1559			#size-cells = <0>;
1560			compatible = "st,stm32h7-spi";
1561			reg = <0x5c001000 0x400>;
1562			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1563			clocks = <&rcc SPI6_K>;
1564			resets = <&rcc SPI6_R>;
1565			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1566			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
1567			dma-names = "rx", "tx";
1568			status = "disabled";
1569		};
1570
1571		i2c4: i2c@5c002000 {
1572			compatible = "st,stm32mp15-i2c";
1573			reg = <0x5c002000 0x400>;
1574			interrupt-names = "event", "error";
1575			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1576				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1577			clocks = <&rcc I2C4_K>;
1578			resets = <&rcc I2C4_R>;
1579			#address-cells = <1>;
1580			#size-cells = <0>;
1581			st,syscfg-fmp = <&syscfg 0x4 0x8>;
1582			wakeup-source;
1583			i2c-analog-filter;
1584			status = "disabled";
1585		};
1586
1587		rtc: rtc@5c004000 {
1588			compatible = "st,stm32mp1-rtc";
1589			reg = <0x5c004000 0x400>;
1590			clocks = <&rcc RTCAPB>, <&rcc RTC>;
1591			clock-names = "pclk", "rtc_ck";
1592			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1593			status = "disabled";
1594		};
1595
1596		bsec: efuse@5c005000 {
1597			compatible = "st,stm32mp15-bsec";
1598			reg = <0x5c005000 0x400>;
1599			#address-cells = <1>;
1600			#size-cells = <1>;
1601			part_number_otp: part_number_otp@4 {
1602				reg = <0x4 0x1>;
1603			};
1604			ts_cal1: calib@5c {
1605				reg = <0x5c 0x2>;
1606			};
1607			ts_cal2: calib@5e {
1608				reg = <0x5e 0x2>;
1609			};
1610		};
1611
1612		i2c6: i2c@5c009000 {
1613			compatible = "st,stm32mp15-i2c";
1614			reg = <0x5c009000 0x400>;
1615			interrupt-names = "event", "error";
1616			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1617				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1618			clocks = <&rcc I2C6_K>;
1619			resets = <&rcc I2C6_R>;
1620			#address-cells = <1>;
1621			#size-cells = <0>;
1622			st,syscfg-fmp = <&syscfg 0x4 0x20>;
1623			wakeup-source;
1624			i2c-analog-filter;
1625			status = "disabled";
1626		};
1627
1628		tamp: tamp@5c00a000 {
1629			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1630			reg = <0x5c00a000 0x400>;
1631		};
1632
1633		/*
1634		 * Break node order to solve dependency probe issue between
1635		 * pinctrl and exti.
1636		 */
1637		pinctrl: pin-controller@50002000 {
1638			#address-cells = <1>;
1639			#size-cells = <1>;
1640			compatible = "st,stm32mp157-pinctrl";
1641			ranges = <0 0x50002000 0xa400>;
1642			interrupt-parent = <&exti>;
1643			st,syscfg = <&exti 0x60 0xff>;
1644			hwlocks = <&hwspinlock 0>;
1645			pins-are-numbered;
1646
1647			gpioa: gpio@50002000 {
1648				gpio-controller;
1649				#gpio-cells = <2>;
1650				interrupt-controller;
1651				#interrupt-cells = <2>;
1652				reg = <0x0 0x400>;
1653				clocks = <&rcc GPIOA>;
1654				st,bank-name = "GPIOA";
1655				status = "disabled";
1656			};
1657
1658			gpiob: gpio@50003000 {
1659				gpio-controller;
1660				#gpio-cells = <2>;
1661				interrupt-controller;
1662				#interrupt-cells = <2>;
1663				reg = <0x1000 0x400>;
1664				clocks = <&rcc GPIOB>;
1665				st,bank-name = "GPIOB";
1666				status = "disabled";
1667			};
1668
1669			gpioc: gpio@50004000 {
1670				gpio-controller;
1671				#gpio-cells = <2>;
1672				interrupt-controller;
1673				#interrupt-cells = <2>;
1674				reg = <0x2000 0x400>;
1675				clocks = <&rcc GPIOC>;
1676				st,bank-name = "GPIOC";
1677				status = "disabled";
1678			};
1679
1680			gpiod: gpio@50005000 {
1681				gpio-controller;
1682				#gpio-cells = <2>;
1683				interrupt-controller;
1684				#interrupt-cells = <2>;
1685				reg = <0x3000 0x400>;
1686				clocks = <&rcc GPIOD>;
1687				st,bank-name = "GPIOD";
1688				status = "disabled";
1689			};
1690
1691			gpioe: gpio@50006000 {
1692				gpio-controller;
1693				#gpio-cells = <2>;
1694				interrupt-controller;
1695				#interrupt-cells = <2>;
1696				reg = <0x4000 0x400>;
1697				clocks = <&rcc GPIOE>;
1698				st,bank-name = "GPIOE";
1699				status = "disabled";
1700			};
1701
1702			gpiof: gpio@50007000 {
1703				gpio-controller;
1704				#gpio-cells = <2>;
1705				interrupt-controller;
1706				#interrupt-cells = <2>;
1707				reg = <0x5000 0x400>;
1708				clocks = <&rcc GPIOF>;
1709				st,bank-name = "GPIOF";
1710				status = "disabled";
1711			};
1712
1713			gpiog: gpio@50008000 {
1714				gpio-controller;
1715				#gpio-cells = <2>;
1716				interrupt-controller;
1717				#interrupt-cells = <2>;
1718				reg = <0x6000 0x400>;
1719				clocks = <&rcc GPIOG>;
1720				st,bank-name = "GPIOG";
1721				status = "disabled";
1722			};
1723
1724			gpioh: gpio@50009000 {
1725				gpio-controller;
1726				#gpio-cells = <2>;
1727				interrupt-controller;
1728				#interrupt-cells = <2>;
1729				reg = <0x7000 0x400>;
1730				clocks = <&rcc GPIOH>;
1731				st,bank-name = "GPIOH";
1732				status = "disabled";
1733			};
1734
1735			gpioi: gpio@5000a000 {
1736				gpio-controller;
1737				#gpio-cells = <2>;
1738				interrupt-controller;
1739				#interrupt-cells = <2>;
1740				reg = <0x8000 0x400>;
1741				clocks = <&rcc GPIOI>;
1742				st,bank-name = "GPIOI";
1743				status = "disabled";
1744			};
1745
1746			gpioj: gpio@5000b000 {
1747				gpio-controller;
1748				#gpio-cells = <2>;
1749				interrupt-controller;
1750				#interrupt-cells = <2>;
1751				reg = <0x9000 0x400>;
1752				clocks = <&rcc GPIOJ>;
1753				st,bank-name = "GPIOJ";
1754				status = "disabled";
1755			};
1756
1757			gpiok: gpio@5000c000 {
1758				gpio-controller;
1759				#gpio-cells = <2>;
1760				interrupt-controller;
1761				#interrupt-cells = <2>;
1762				reg = <0xa000 0x400>;
1763				clocks = <&rcc GPIOK>;
1764				st,bank-name = "GPIOK";
1765				status = "disabled";
1766			};
1767		};
1768
1769		pinctrl_z: pin-controller-z@54004000 {
1770			#address-cells = <1>;
1771			#size-cells = <1>;
1772			compatible = "st,stm32mp157-z-pinctrl";
1773			ranges = <0 0x54004000 0x400>;
1774			pins-are-numbered;
1775			interrupt-parent = <&exti>;
1776			st,syscfg = <&exti 0x60 0xff>;
1777			hwlocks = <&hwspinlock 0>;
1778
1779			gpioz: gpio@54004000 {
1780				gpio-controller;
1781				#gpio-cells = <2>;
1782				interrupt-controller;
1783				#interrupt-cells = <2>;
1784				reg = <0 0x400>;
1785				clocks = <&rcc GPIOZ>;
1786				st,bank-name = "GPIOZ";
1787				st,bank-ioport = <11>;
1788				status = "disabled";
1789			};
1790		};
1791	};
1792
1793	mlahb: ahb {
1794		compatible = "st,mlahb", "simple-bus";
1795		#address-cells = <1>;
1796		#size-cells = <1>;
1797		ranges;
1798		dma-ranges = <0x00000000 0x38000000 0x10000>,
1799			     <0x10000000 0x10000000 0x60000>,
1800			     <0x30000000 0x30000000 0x60000>;
1801
1802		m4_rproc: m4@10000000 {
1803			compatible = "st,stm32mp1-m4";
1804			reg = <0x10000000 0x40000>,
1805			      <0x30000000 0x40000>,
1806			      <0x38000000 0x10000>;
1807			resets = <&rcc MCU_R>;
1808			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1809			st,syscfg-tz = <&rcc 0x000 0x1>;
1810			st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1811			st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1812			st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1813			status = "disabled";
1814		};
1815	};
1816};
1817