1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp15-u-boot.dtsi"
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		i2c3 = &i2c4;
13		usb0 = &usbotg_hs;
14	};
15	config {
16		u-boot,boot-led = "heartbeat";
17		u-boot,error-led = "error";
18		u-boot,mmc-env-partition = "fip";
19		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
20		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
21		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
22	};
23
24#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
25	config {
26		u-boot,mmc-env-partition = "ssbl";
27	};
28#endif
29
30#ifdef CONFIG_STM32MP15x_STM32IMAGE
31	/* only needed for boot with TF-A, witout FIP support */
32	firmware {
33		optee {
34			compatible = "linaro,optee-tz";
35			method = "smc";
36		};
37	};
38
39	reserved-memory {
40		u-boot,dm-spl;
41
42		optee@de000000 {
43			reg = <0xde000000 0x02000000>;
44			no-map;
45			u-boot,dm-spl;
46		};
47	};
48#endif
49
50	led {
51		red {
52			label = "error";
53			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
54			default-state = "off";
55			status = "okay";
56		};
57	};
58};
59
60&adc {
61	status = "okay";
62};
63
64&clk_hse {
65	st,digbypass;
66};
67
68&i2c4 {
69	u-boot,dm-pre-reloc;
70};
71
72&i2c4_pins_a {
73	u-boot,dm-pre-reloc;
74	pins {
75		u-boot,dm-pre-reloc;
76	};
77};
78
79&pmic {
80	u-boot,dm-pre-reloc;
81};
82
83&rcc {
84	st,clksrc = <
85		CLK_MPU_PLL1P
86		CLK_AXI_PLL2P
87		CLK_MCU_PLL3P
88		CLK_PLL12_HSE
89		CLK_PLL3_HSE
90		CLK_PLL4_HSE
91		CLK_RTC_LSE
92		CLK_MCO1_DISABLED
93		CLK_MCO2_DISABLED
94	>;
95
96	st,clkdiv = <
97		1 /*MPU*/
98		0 /*AXI*/
99		0 /*MCU*/
100		1 /*APB1*/
101		1 /*APB2*/
102		1 /*APB3*/
103		1 /*APB4*/
104		2 /*APB5*/
105		23 /*RTC*/
106		0 /*MCO1*/
107		0 /*MCO2*/
108	>;
109
110	st,pkcs = <
111		CLK_CKPER_HSE
112		CLK_FMC_ACLK
113		CLK_QSPI_ACLK
114		CLK_ETH_DISABLED
115		CLK_SDMMC12_PLL4P
116		CLK_DSI_DSIPLL
117		CLK_STGEN_HSE
118		CLK_USBPHY_HSE
119		CLK_SPI2S1_PLL3Q
120		CLK_SPI2S23_PLL3Q
121		CLK_SPI45_HSI
122		CLK_SPI6_HSI
123		CLK_I2C46_HSI
124		CLK_SDMMC3_PLL4P
125		CLK_USBO_USBPHY
126		CLK_ADC_CKPER
127		CLK_CEC_LSE
128		CLK_I2C12_HSI
129		CLK_I2C35_HSI
130		CLK_UART1_HSI
131		CLK_UART24_HSI
132		CLK_UART35_HSI
133		CLK_UART6_HSI
134		CLK_UART78_HSI
135		CLK_SPDIF_PLL4P
136		CLK_FDCAN_PLL4R
137		CLK_SAI1_PLL3Q
138		CLK_SAI2_PLL3Q
139		CLK_SAI3_PLL3Q
140		CLK_SAI4_PLL3Q
141		CLK_RNG1_LSI
142		CLK_RNG2_LSI
143		CLK_LPTIM1_PCLK1
144		CLK_LPTIM23_PCLK3
145		CLK_LPTIM45_LSE
146	>;
147
148	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
149	pll2: st,pll@1 {
150		compatible = "st,stm32mp1-pll";
151		reg = <1>;
152		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
153		frac = < 0x1400 >;
154		u-boot,dm-pre-reloc;
155	};
156
157	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
158	pll3: st,pll@2 {
159		compatible = "st,stm32mp1-pll";
160		reg = <2>;
161		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
162		frac = < 0x1a04 >;
163		u-boot,dm-pre-reloc;
164	};
165
166	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
167	pll4: st,pll@3 {
168		compatible = "st,stm32mp1-pll";
169		reg = <3>;
170		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
171		u-boot,dm-pre-reloc;
172	};
173};
174
175&sdmmc1 {
176	u-boot,dm-spl;
177};
178
179&sdmmc1_b4_pins_a {
180	u-boot,dm-spl;
181	pins1 {
182		u-boot,dm-spl;
183	};
184	pins2 {
185		u-boot,dm-spl;
186	};
187};
188
189&uart4 {
190	u-boot,dm-pre-reloc;
191};
192
193&uart4_pins_a {
194	u-boot,dm-pre-reloc;
195	pins1 {
196		u-boot,dm-pre-reloc;
197	};
198	pins2 {
199		u-boot,dm-pre-reloc;
200		/* pull-up on rx to avoid floating level */
201		bias-pull-up;
202	};
203};
204
205&usbotg_hs {
206	u-boot,force-b-session-valid;
207};
208