1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/reset/sun50i-h616-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0>; 25 enable-method = "psci"; 26 clocks = <&ccu CLK_CPUX>; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <1>; 33 enable-method = "psci"; 34 clocks = <&ccu CLK_CPUX>; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <2>; 41 enable-method = "psci"; 42 clocks = <&ccu CLK_CPUX>; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 clocks = <&ccu CLK_CPUX>; 51 }; 52 }; 53 54 osc24M: osc24M_clk { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <24000000>; 58 clock-output-names = "osc24M"; 59 }; 60 61 pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 psci { 71 compatible = "arm,psci-0.2"; 72 method = "smc"; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 arm,no-tick-in-suspend; 78 interrupts = <GIC_PPI 13 79 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 11 83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 10 85 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 86 }; 87 88 soc { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0x0 0x0 0x0 0x40000000>; 93 94 syscon: syscon@3000000 { 95 compatible = "allwinner,sun50i-h616-system-control"; 96 reg = <0x03000000 0x1000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 sram_c: sram@28000 { 102 compatible = "mmio-sram"; 103 reg = <0x00028000 0x30000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0x00028000 0x30000>; 107 }; 108 }; 109 110 ccu: clock@3001000 { 111 compatible = "allwinner,sun50i-h616-ccu"; 112 reg = <0x03001000 0x1000>; 113 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 114 clock-names = "hosc", "losc", "iosc"; 115 #clock-cells = <1>; 116 #reset-cells = <1>; 117 }; 118 119 watchdog: watchdog@30090a0 { 120 compatible = "allwinner,sun50i-h616-wdt", 121 "allwinner,sun6i-a31-wdt"; 122 reg = <0x030090a0 0x20>; 123 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&osc24M>; 125 }; 126 127 pio: pinctrl@300b000 { 128 compatible = "allwinner,sun50i-h616-pinctrl"; 129 reg = <0x0300b000 0x400>; 130 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 139 clock-names = "apb", "hosc", "losc"; 140 gpio-controller; 141 #gpio-cells = <3>; 142 interrupt-controller; 143 #interrupt-cells = <3>; 144 145 ext_rgmii_pins: rgmii-pins { 146 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 147 "PI5", "PI7", "PI8", "PI9", "PI10", 148 "PI11", "PI12", "PI13", "PI14", "PI15", 149 "PI16"; 150 function = "emac0"; 151 drive-strength = <40>; 152 }; 153 154 i2c0_pins: i2c0-pins { 155 pins = "PI6", "PI7"; 156 function = "i2c0"; 157 }; 158 159 i2c3_ph_pins: i2c3-ph-pins { 160 pins = "PH4", "PH5"; 161 function = "i2c3"; 162 }; 163 164 ir_rx_pin: ir_rx_pin { 165 pins = "PH10"; 166 function = "ir_rx"; 167 }; 168 169 mmc0_pins: mmc0-pins { 170 pins = "PF0", "PF1", "PF2", "PF3", 171 "PF4", "PF5"; 172 function = "mmc0"; 173 drive-strength = <30>; 174 bias-pull-up; 175 }; 176 177 mmc1_pins: mmc1-pins { 178 pins = "PG0", "PG1", "PG2", "PG3", 179 "PG4", "PG5"; 180 function = "mmc1"; 181 drive-strength = <30>; 182 bias-pull-up; 183 }; 184 185 mmc2_pins: mmc2-pins { 186 pins = "PC0", "PC1", "PC5", "PC6", 187 "PC8", "PC9", "PC10", "PC11", 188 "PC13", "PC14", "PC15", "PC16"; 189 function = "mmc2"; 190 drive-strength = <30>; 191 bias-pull-up; 192 }; 193 194 spi0_pins: spi0-pins { 195 pins = "PC0", "PC2", "PC3", "PC4"; 196 function = "spi0"; 197 }; 198 199 spi1_pins: spi1-pins { 200 pins = "PH6", "PH7", "PH8"; 201 function = "spi1"; 202 }; 203 204 spi1_cs_pin: spi1-cs-pin { 205 pins = "PH5"; 206 function = "spi1"; 207 }; 208 209 uart0_ph_pins: uart0-ph-pins { 210 pins = "PH0", "PH1"; 211 function = "uart0"; 212 }; 213 214 uart1_pins: uart1-pins { 215 pins = "PG6", "PG7"; 216 function = "uart1"; 217 }; 218 219 uart1_rts_cts_pins: uart1-rts-cts-pins { 220 pins = "PG8", "PG9"; 221 function = "uart1"; 222 }; 223 }; 224 225 gic: interrupt-controller@3021000 { 226 compatible = "arm,gic-400"; 227 reg = <0x03021000 0x1000>, 228 <0x03022000 0x2000>, 229 <0x03024000 0x2000>, 230 <0x03026000 0x2000>; 231 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 232 interrupt-controller; 233 #interrupt-cells = <3>; 234 }; 235 236 mmc0: mmc@4020000 { 237 compatible = "allwinner,sun50i-h616-mmc", 238 "allwinner,sun50i-a100-mmc"; 239 reg = <0x04020000 0x1000>; 240 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 241 clock-names = "ahb", "mmc"; 242 resets = <&ccu RST_BUS_MMC0>; 243 reset-names = "ahb"; 244 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&mmc0_pins>; 247 status = "disabled"; 248 cap-sd-highspeed; 249 cap-mmc-highspeed; 250 mmc-ddr-3_3v; 251 mmc-ddr-1_8v; 252 cap-sdio-irq; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 }; 256 257 mmc1: mmc@4021000 { 258 compatible = "allwinner,sun50i-h616-mmc", 259 "allwinner,sun50i-a100-mmc"; 260 reg = <0x04021000 0x1000>; 261 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 262 clock-names = "ahb", "mmc"; 263 resets = <&ccu RST_BUS_MMC1>; 264 reset-names = "ahb"; 265 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&mmc1_pins>; 268 status = "disabled"; 269 cap-sd-highspeed; 270 cap-mmc-highspeed; 271 mmc-ddr-3_3v; 272 mmc-ddr-1_8v; 273 cap-sdio-irq; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 }; 277 278 mmc2: mmc@4022000 { 279 compatible = "allwinner,sun50i-h616-emmc", 280 "allwinner,sun50i-a100-emmc"; 281 reg = <0x04022000 0x1000>; 282 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 283 clock-names = "ahb", "mmc"; 284 resets = <&ccu RST_BUS_MMC2>; 285 reset-names = "ahb"; 286 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&mmc2_pins>; 289 status = "disabled"; 290 cap-sd-highspeed; 291 cap-mmc-highspeed; 292 mmc-ddr-3_3v; 293 mmc-ddr-1_8v; 294 cap-sdio-irq; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 }; 298 299 uart0: serial@5000000 { 300 compatible = "snps,dw-apb-uart"; 301 reg = <0x05000000 0x400>; 302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 303 reg-shift = <2>; 304 reg-io-width = <4>; 305 clocks = <&ccu CLK_BUS_UART0>; 306 resets = <&ccu RST_BUS_UART0>; 307 status = "disabled"; 308 }; 309 310 uart1: serial@5000400 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0x05000400 0x400>; 313 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 314 reg-shift = <2>; 315 reg-io-width = <4>; 316 clocks = <&ccu CLK_BUS_UART1>; 317 resets = <&ccu RST_BUS_UART1>; 318 status = "disabled"; 319 }; 320 321 uart2: serial@5000800 { 322 compatible = "snps,dw-apb-uart"; 323 reg = <0x05000800 0x400>; 324 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 325 reg-shift = <2>; 326 reg-io-width = <4>; 327 clocks = <&ccu CLK_BUS_UART2>; 328 resets = <&ccu RST_BUS_UART2>; 329 status = "disabled"; 330 }; 331 332 uart3: serial@5000c00 { 333 compatible = "snps,dw-apb-uart"; 334 reg = <0x05000c00 0x400>; 335 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 336 reg-shift = <2>; 337 reg-io-width = <4>; 338 clocks = <&ccu CLK_BUS_UART3>; 339 resets = <&ccu RST_BUS_UART3>; 340 status = "disabled"; 341 }; 342 343 uart4: serial@5001000 { 344 compatible = "snps,dw-apb-uart"; 345 reg = <0x05001000 0x400>; 346 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 347 reg-shift = <2>; 348 reg-io-width = <4>; 349 clocks = <&ccu CLK_BUS_UART4>; 350 resets = <&ccu RST_BUS_UART4>; 351 status = "disabled"; 352 }; 353 354 uart5: serial@5001400 { 355 compatible = "snps,dw-apb-uart"; 356 reg = <0x05001400 0x400>; 357 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 358 reg-shift = <2>; 359 reg-io-width = <4>; 360 clocks = <&ccu CLK_BUS_UART5>; 361 resets = <&ccu RST_BUS_UART5>; 362 status = "disabled"; 363 }; 364 365 i2c0: i2c@5002000 { 366 compatible = "allwinner,sun50i-h616-i2c", 367 "allwinner,sun6i-a31-i2c"; 368 reg = <0x05002000 0x400>; 369 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&ccu CLK_BUS_I2C0>; 371 resets = <&ccu RST_BUS_I2C0>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&i2c0_pins>; 374 status = "disabled"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 }; 378 379 i2c1: i2c@5002400 { 380 compatible = "allwinner,sun50i-h616-i2c", 381 "allwinner,sun6i-a31-i2c"; 382 reg = <0x05002400 0x400>; 383 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&ccu CLK_BUS_I2C1>; 385 resets = <&ccu RST_BUS_I2C1>; 386 status = "disabled"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 }; 390 391 i2c2: i2c@5002800 { 392 compatible = "allwinner,sun50i-h616-i2c", 393 "allwinner,sun6i-a31-i2c"; 394 reg = <0x05002800 0x400>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&ccu CLK_BUS_I2C2>; 397 resets = <&ccu RST_BUS_I2C2>; 398 status = "disabled"; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 }; 402 403 i2c3: i2c@5002c00 { 404 compatible = "allwinner,sun50i-h616-i2c", 405 "allwinner,sun6i-a31-i2c"; 406 reg = <0x05002c00 0x400>; 407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&ccu CLK_BUS_I2C3>; 409 resets = <&ccu RST_BUS_I2C3>; 410 status = "disabled"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 }; 414 415 i2c4: i2c@5003000 { 416 compatible = "allwinner,sun50i-h616-i2c", 417 "allwinner,sun6i-a31-i2c"; 418 reg = <0x05003000 0x400>; 419 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&ccu CLK_BUS_I2C4>; 421 resets = <&ccu RST_BUS_I2C4>; 422 status = "disabled"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 427 spi0: spi@5010000 { 428 compatible = "allwinner,sun50i-h616-spi", 429 "allwinner,sun8i-h3-spi"; 430 reg = <0x05010000 0x1000>; 431 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 433 clock-names = "ahb", "mod"; 434 resets = <&ccu RST_BUS_SPI0>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&spi0_pins>; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 442 spi1: spi@5011000 { 443 compatible = "allwinner,sun50i-h616-spi", 444 "allwinner,sun8i-h3-spi"; 445 reg = <0x05011000 0x1000>; 446 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 448 clock-names = "ahb", "mod"; 449 resets = <&ccu RST_BUS_SPI1>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&spi1_pins>; 452 status = "disabled"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 }; 456 457 emac0: ethernet@5020000 { 458 compatible = "allwinner,sun50i-h616-emac", 459 "allwinner,sun50i-a64-emac"; 460 syscon = <&syscon>; 461 reg = <0x05020000 0x10000>; 462 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "macirq"; 464 resets = <&ccu RST_BUS_EMAC0>; 465 reset-names = "stmmaceth"; 466 clocks = <&ccu CLK_BUS_EMAC0>; 467 clock-names = "stmmaceth"; 468 status = "disabled"; 469 470 mdio0: mdio { 471 compatible = "snps,dwmac-mdio"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 }; 476 477 emac1: ethernet@5030000 { 478 compatible = "allwinner,sun50i-h616-emac"; 479 syscon = <&syscon 1>; 480 reg = <0x05030000 0x10000>; 481 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "macirq"; 483 resets = <&ccu RST_BUS_EMAC1>; 484 reset-names = "stmmaceth"; 485 clocks = <&ccu CLK_BUS_EMAC1>; 486 clock-names = "stmmaceth"; 487 status = "disabled"; 488 489 mdio1: mdio { 490 compatible = "snps,dwmac-mdio"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 }; 494 }; 495 496 usbotg: usb@5100000 { 497 compatible = "allwinner,sun50i-h616-musb", 498 "allwinner,sun8i-h3-musb"; 499 reg = <0x05100000 0x0400>; 500 clocks = <&ccu CLK_BUS_OTG>; 501 resets = <&ccu RST_BUS_OTG>; 502 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "mc"; 504 phys = <&usbphy 0>; 505 phy-names = "usb"; 506 extcon = <&usbphy 0>; 507 status = "disabled"; 508 }; 509 510 usbphy: phy@5100400 { 511 compatible = "allwinner,sun50i-h616-usb-phy"; 512 reg = <0x05100400 0x24>, 513 <0x05101800 0x14>, 514 <0x05200800 0x14>, 515 <0x05310800 0x14>, 516 <0x05311800 0x14>; 517 reg-names = "phy_ctrl", 518 "pmu0", 519 "pmu1", 520 "pmu2", 521 "pmu3"; 522 clocks = <&ccu CLK_USB_PHY0>, 523 <&ccu CLK_USB_PHY1>, 524 <&ccu CLK_USB_PHY2>, 525 <&ccu CLK_USB_PHY3>; 526 clock-names = "usb0_phy", 527 "usb1_phy", 528 "usb2_phy", 529 "usb3_phy"; 530 resets = <&ccu RST_USB_PHY0>, 531 <&ccu RST_USB_PHY1>, 532 <&ccu RST_USB_PHY2>, 533 <&ccu RST_USB_PHY3>; 534 reset-names = "usb0_reset", 535 "usb1_reset", 536 "usb2_reset", 537 "usb3_reset"; 538 status = "disabled"; 539 #phy-cells = <1>; 540 }; 541 542 ehci0: usb@5101000 { 543 compatible = "allwinner,sun50i-h616-ehci", 544 "generic-ehci"; 545 reg = <0x05101000 0x100>; 546 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&ccu CLK_BUS_OHCI0>, 548 <&ccu CLK_BUS_EHCI0>, 549 <&ccu CLK_USB_OHCI0>; 550 resets = <&ccu RST_BUS_OHCI0>, 551 <&ccu RST_BUS_EHCI0>; 552 phys = <&usbphy 0>; 553 phy-names = "usb"; 554 status = "disabled"; 555 }; 556 557 ohci0: usb@5101400 { 558 compatible = "allwinner,sun50i-h616-ohci", 559 "generic-ohci"; 560 reg = <0x05101400 0x100>; 561 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&ccu CLK_BUS_OHCI0>, 563 <&ccu CLK_USB_OHCI0>; 564 resets = <&ccu RST_BUS_OHCI0>; 565 phys = <&usbphy 0>; 566 phy-names = "usb"; 567 status = "disabled"; 568 }; 569 570 ehci1: usb@5200000 { 571 compatible = "allwinner,sun50i-h616-ehci", 572 "generic-ehci"; 573 reg = <0x05200000 0x100>; 574 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_BUS_OHCI1>, 576 <&ccu CLK_BUS_EHCI1>, 577 <&ccu CLK_USB_OHCI1>; 578 resets = <&ccu RST_BUS_OHCI1>, 579 <&ccu RST_BUS_EHCI1>; 580 phys = <&usbphy 1>; 581 phy-names = "usb"; 582 status = "disabled"; 583 }; 584 585 ohci1: usb@5200400 { 586 compatible = "allwinner,sun50i-h616-ohci", 587 "generic-ohci"; 588 reg = <0x05200400 0x100>; 589 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&ccu CLK_BUS_OHCI1>, 591 <&ccu CLK_USB_OHCI1>; 592 resets = <&ccu RST_BUS_OHCI1>; 593 phys = <&usbphy 1>; 594 phy-names = "usb"; 595 status = "disabled"; 596 }; 597 598 ehci2: usb@5310000 { 599 compatible = "allwinner,sun50i-h616-ehci", 600 "generic-ehci"; 601 reg = <0x05310000 0x100>; 602 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&ccu CLK_BUS_OHCI2>, 604 <&ccu CLK_BUS_EHCI2>, 605 <&ccu CLK_USB_OHCI2>; 606 resets = <&ccu RST_BUS_OHCI2>, 607 <&ccu RST_BUS_EHCI2>; 608 phys = <&usbphy 2>; 609 phy-names = "usb"; 610 status = "disabled"; 611 }; 612 613 ohci2: usb@5310400 { 614 compatible = "allwinner,sun50i-h616-ohci", 615 "generic-ohci"; 616 reg = <0x05310400 0x100>; 617 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&ccu CLK_BUS_OHCI2>, 619 <&ccu CLK_USB_OHCI2>; 620 resets = <&ccu RST_BUS_OHCI2>; 621 phys = <&usbphy 2>; 622 phy-names = "usb"; 623 status = "disabled"; 624 }; 625 626 ehci3: usb@5311000 { 627 compatible = "allwinner,sun50i-h616-ehci", 628 "generic-ehci"; 629 reg = <0x05311000 0x100>; 630 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&ccu CLK_BUS_OHCI3>, 632 <&ccu CLK_BUS_EHCI3>, 633 <&ccu CLK_USB_OHCI3>; 634 resets = <&ccu RST_BUS_OHCI3>, 635 <&ccu RST_BUS_EHCI3>; 636 phys = <&usbphy 3>; 637 phy-names = "usb"; 638 status = "disabled"; 639 }; 640 641 ohci3: usb@5311400 { 642 compatible = "allwinner,sun50i-h616-ohci", 643 "generic-ohci"; 644 reg = <0x05311400 0x100>; 645 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&ccu CLK_BUS_OHCI3>, 647 <&ccu CLK_USB_OHCI3>; 648 resets = <&ccu RST_BUS_OHCI3>; 649 phys = <&usbphy 3>; 650 phy-names = "usb"; 651 status = "disabled"; 652 }; 653 654 rtc: rtc@7000000 { 655 compatible = "allwinner,sun50i-h616-rtc", 656 "allwinner,sun50i-h6-rtc"; 657 reg = <0x07000000 0x400>; 658 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 660 clock-output-names = "osc32k", "osc32k-out", "iosc"; 661 #clock-cells = <1>; 662 }; 663 664 r_ccu: clock@7010000 { 665 compatible = "allwinner,sun50i-h616-r-ccu"; 666 reg = <0x07010000 0x400>; 667 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 668 <&ccu CLK_PLL_PERIPH0>; 669 clock-names = "hosc", "losc", "iosc", "pll-periph"; 670 #clock-cells = <1>; 671 #reset-cells = <1>; 672 }; 673 674 r_pio: pinctrl@7022000 { 675 compatible = "allwinner,sun50i-h616-r-pinctrl"; 676 reg = <0x07022000 0x400>; 677 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 679 clock-names = "apb", "hosc", "losc"; 680 gpio-controller; 681 #gpio-cells = <3>; 682 interrupt-controller; 683 #interrupt-cells = <3>; 684 685 r_i2c_pins: r-i2c-pins { 686 pins = "PL0", "PL1"; 687 function = "s_i2c"; 688 }; 689 690 r_rsb_pins: r-rsb-pins { 691 pins = "PL0", "PL1"; 692 function = "s_rsb"; 693 }; 694 }; 695 696 ir: ir@7040000 { 697 compatible = "allwinner,sun50i-h616-ir", 698 "allwinner,sun6i-a31-ir"; 699 reg = <0x07040000 0x400>; 700 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&r_ccu CLK_R_APB1_IR>, 702 <&r_ccu CLK_IR>; 703 clock-names = "apb", "ir"; 704 resets = <&r_ccu RST_R_APB1_IR>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&ir_rx_pin>; 707 status = "disabled"; 708 }; 709 710 r_i2c: i2c@7081400 { 711 compatible = "allwinner,sun50i-h616-i2c", 712 "allwinner,sun6i-a31-i2c"; 713 reg = <0x07081400 0x400>; 714 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&r_ccu CLK_R_APB2_I2C>; 716 resets = <&r_ccu RST_R_APB2_I2C>; 717 status = "disabled"; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 }; 721 722 r_rsb: rsb@7083000 { 723 compatible = "allwinner,sun50i-h616-rsb", 724 "allwinner,sun8i-a23-rsb"; 725 reg = <0x07083000 0x400>; 726 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&r_ccu CLK_R_APB2_RSB>; 728 clock-frequency = <3000000>; 729 resets = <&r_ccu RST_R_APB2_RSB>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&r_rsb_pins>; 732 status = "disabled"; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 }; 736 }; 737}; 738