1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
11/ {
12	fclk0: fclk0 {
13		status = "okay";
14		compatible = "xlnx,fclk";
15		clocks = <&zynqmp_clk PL0_REF>;
16	};
17
18	fclk1: fclk1 {
19		status = "okay";
20		compatible = "xlnx,fclk";
21		clocks = <&zynqmp_clk PL1_REF>;
22	};
23
24	fclk2: fclk2 {
25		status = "okay";
26		compatible = "xlnx,fclk";
27		clocks = <&zynqmp_clk PL2_REF>;
28	};
29
30	fclk3: fclk3 {
31		status = "okay";
32		compatible = "xlnx,fclk";
33		clocks = <&zynqmp_clk PL3_REF>;
34	};
35
36	pss_ref_clk: pss_ref_clk {
37		u-boot,dm-pre-reloc;
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <33333333>;
41	};
42
43	video_clk: video_clk {
44		u-boot,dm-pre-reloc;
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48	};
49
50	pss_alt_ref_clk: pss_alt_ref_clk {
51		u-boot,dm-pre-reloc;
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <0>;
55	};
56
57	gt_crx_ref_clk: gt_crx_ref_clk {
58		u-boot,dm-pre-reloc;
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <108000000>;
62	};
63
64	aux_ref_clk: aux_ref_clk {
65		u-boot,dm-pre-reloc;
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <27000000>;
69	};
70};
71
72&zynqmp_firmware {
73	zynqmp_clk: clock-controller {
74		u-boot,dm-pre-reloc;
75		#clock-cells = <1>;
76		compatible = "xlnx,zynqmp-clk";
77		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
78			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
79		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
80			      "aux_ref_clk", "gt_crx_ref_clk";
81	};
82};
83
84&can0 {
85	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
86};
87
88&can1 {
89	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
90};
91
92&cpu0 {
93	clocks = <&zynqmp_clk ACPU>;
94};
95
96&fpd_dma_chan1 {
97	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
98};
99
100&fpd_dma_chan2 {
101	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
102};
103
104&fpd_dma_chan3 {
105	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
106};
107
108&fpd_dma_chan4 {
109	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
110};
111
112&fpd_dma_chan5 {
113	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
114};
115
116&fpd_dma_chan6 {
117	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
118};
119
120&fpd_dma_chan7 {
121	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
122};
123
124&fpd_dma_chan8 {
125	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
126};
127
128&gpu {
129	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
130};
131
132&lpd_dma_chan1 {
133	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
134};
135
136&lpd_dma_chan2 {
137	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
138};
139
140&lpd_dma_chan3 {
141	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
142};
143
144&lpd_dma_chan4 {
145	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
146};
147
148&lpd_dma_chan5 {
149	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
150};
151
152&lpd_dma_chan6 {
153	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
154};
155
156&lpd_dma_chan7 {
157	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
158};
159
160&lpd_dma_chan8 {
161	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
162};
163
164&nand0 {
165	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
166};
167
168&gem0 {
169	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
170		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
171		 <&zynqmp_clk GEM_TSU>;
172	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
173};
174
175&gem1 {
176	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
177		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
178		 <&zynqmp_clk GEM_TSU>;
179	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
180};
181
182&gem2 {
183	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
184		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
185		 <&zynqmp_clk GEM_TSU>;
186	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
187};
188
189&gem3 {
190	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
191		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
192		 <&zynqmp_clk GEM_TSU>;
193	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
194};
195
196&gpio {
197	clocks = <&zynqmp_clk LPD_LSBUS>;
198};
199
200&i2c0 {
201	clocks = <&zynqmp_clk I2C0_REF>;
202};
203
204&i2c1 {
205	clocks = <&zynqmp_clk I2C1_REF>;
206};
207
208&pcie {
209	clocks = <&zynqmp_clk PCIE_REF>;
210};
211
212&qspi {
213	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
214};
215
216&sata {
217	clocks = <&zynqmp_clk SATA_REF>;
218};
219
220&sdhci0 {
221	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
222};
223
224&sdhci1 {
225	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
226};
227
228&spi0 {
229	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
230};
231
232&spi1 {
233	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
234};
235
236&ttc0 {
237	clocks = <&zynqmp_clk LPD_LSBUS>;
238};
239
240&ttc1 {
241	clocks = <&zynqmp_clk LPD_LSBUS>;
242};
243
244&ttc2 {
245	clocks = <&zynqmp_clk LPD_LSBUS>;
246};
247
248&ttc3 {
249	clocks = <&zynqmp_clk LPD_LSBUS>;
250};
251
252&uart0 {
253	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
254};
255
256&uart1 {
257	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
258};
259
260&usb0 {
261	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
262};
263
264&usb1 {
265	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
266};
267
268&watchdog0 {
269	clocks = <&zynqmp_clk WDT>;
270};
271
272&lpd_watchdog {
273	clocks = <&zynqmp_clk LPD_WDT>;
274};
275
276&xilinx_ams {
277	clocks = <&zynqmp_clk AMS_REF>;
278};
279
280&zynqmp_pcap {
281	clocks = <&zynqmp_clk PCAP>;
282};
283
284&zynqmp_dpdma {
285	clocks = <&zynqmp_clk DPDMA_REF>;
286};
287
288&zynqmp_dpsub {
289	clocks = <&zynqmp_clk TOPSW_LSBUS>,
290		 <&zynqmp_clk DP_AUDIO_REF>,
291		 <&zynqmp_clk DP_VIDEO_REF>;
292};
293