1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal a2197 RevA System Controller on MGT 4 * 5 * (C) Copyright 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9/dts-v1/; 10 11#include "zynqmp.dtsi" 12#include "zynqmp-clk-ccf.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Versal System Controller on a2197 MGT Char board RevA"; 17 compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", 18 "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 19 20 aliases { 21 ethernet0 = &gem0; 22 i2c0 = &i2c0; 23 mmc0 = &sdhci0; 24 nvmem0 = &eeprom; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &dcc; 28 usb0 = &usb0; 29 }; 30 31 chosen { 32 bootargs = "earlycon"; 33 stdout-path = "serial0:115200n8"; 34 }; 35 36 memory@0 { 37 device_type = "memory"; 38 reg = <0x0 0x0 0x0 0x80000000>; 39 }; 40 41 ina226-u74 { 42 compatible = "iio-hwmon"; 43 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 44 }; 45 ina226-u75 { 46 compatible = "iio-hwmon"; 47 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 48 }; 49 ina226-u78 { 50 compatible = "iio-hwmon"; 51 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 52 }; 53 ina226-u79 { 54 compatible = "iio-hwmon"; 55 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 56 }; 57 ina226-u82 { 58 compatible = "iio-hwmon"; 59 io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; 60 }; 61 ina226-u84 { 62 compatible = "iio-hwmon"; 63 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 64 }; 65}; 66 67&sdhci0 { /* emmc MIO 13-23 16GB */ 68 status = "okay"; 69 non-removable; 70 disable-wp; 71 bus-width = <8>; 72 xlnx,mio-bank = <0>; 73}; 74 75&uart0 { /* uart0 MIO38-39 */ 76 status = "okay"; 77}; 78 79&gem0 { /* eth MDIO 76/77 */ 80 status = "okay"; 81 phy-handle = <&phy0>; 82 phy-mode = "sgmii"; 83 is-internal-pcspma; 84 phy0: ethernet-phy@0 { /* marwell m88e1512 */ 85 reg = <0>; 86 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 87/* xlnx,phy-type = <PHY_TYPE_SGMII>; */ 88 }; 89}; 90 91&gpio { 92 status = "okay"; 93 gpio-line-names = "", "", "", "", "", /* 0 - 4 */ 94 "", "", "", "", "", /* 5 - 9 */ 95 "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ 96 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ 97 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ 98 "", "", "", "", "", /* 25 - 29 */ 99 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ 100 "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ 101 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ 102 "", "", "", "", "", /* 45 - 49 */ 103 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ 104 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ 105 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ 106 "", "", "", "", "", /* 65 - 69 */ 107 "", "", "", "", "", /* 70 - 74 */ 108 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ 109 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ 110 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ 111 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ 112 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ 113 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ 114 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ 115 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ 116 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ 117 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ 118 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ 119 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ 120 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ 121 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ 122 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ 123 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ 124 "", "", "", "", "", /* 150 - 154 */ 125 "", "", "", "", "", /* 155 - 159 */ 126 "", "", "", "", "", /* 160 - 164 */ 127 "", "", "", "", "", /* 165 - 169 */ 128 "", "", "", ""; /* 170 - 174 */ 129}; 130 131&i2c0 { /* MIO 34-35 - can't stay here */ 132 status = "okay"; 133 clock-frequency = <400000>; 134 scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; 135 sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; 136 i2c-mux@74 { /* u94 */ 137 compatible = "nxp,pca9548"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 reg = <0x74>; 141 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ 142 i2c@0 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 reg = <0>; 146 /* Use for storing information about SC board */ 147 eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ 148 compatible = "atmel,24c32"; 149 reg = <0x50>; 150 }; 151 }; 152 i2c@1 { /* CM_I2C_SCL - Samtec */ 153 #address-cells = <1>; 154 #size-cells = <0>; 155 reg = <1>; 156 }; 157 i2c@2 { /* PMBUS - AFX_PMBUS */ 158 #address-cells = <1>; 159 #size-cells = <0>; 160 reg = <2>; 161 tps544@d { /* u85 */ 162 compatible = "ti,tps544b25"; 163 reg = <0xd>; 164 }; 165 tps544@10 { /* u73 */ 166 compatible = "ti,tps544b25"; 167 reg = <0x10>; 168 }; 169 tps544@11 { /* u76 */ 170 compatible = "ti,tps544b25"; 171 reg = <0x11>; 172 }; 173 tps544@12 { /* u77 */ 174 compatible = "ti,tps544b25"; 175 reg = <0x12>; 176 }; 177 tps544@13 { /* u80 */ 178 compatible = "ti,tps544b25"; 179 reg = <0x13>; 180 }; 181 tps544@14 { /* u81 */ 182 compatible = "ti,tps544b25"; 183 reg = <0x14>; 184 }; 185 tps544@15 { /* u83 */ 186 compatible = "ti,tps544b25"; 187 reg = <0x15>; 188 }; 189 tps544@16 { /* u63 */ 190 compatible = "ti,tps544b25"; 191 reg = <0x16>; 192 }; 193 tps544@17 { /* u66 */ 194 compatible = "ti,tps544b25"; 195 reg = <0x17>; 196 }; 197 tps544@18 { /* u67 */ 198 compatible = "ti,tps544b25"; 199 reg = <0x18>; 200 }; 201 tps544@19 { /* u69 */ 202 compatible = "ti,tps544b25"; 203 reg = <0x19>; 204 }; 205 tps544@1d { /* u88 */ 206 compatible = "ti,tps544b25"; 207 reg = <0x1d>; 208 }; 209 tps544@1e { /* u89 */ 210 compatible = "ti,tps544b25"; 211 reg = <0x1e>; 212 }; 213 tps544@1f { /* u87 */ 214 compatible = "ti,tps544b25"; 215 reg = <0x1f>; 216 }; 217 tps544@20 { /* u71 */ 218 compatible = "ti,tps544b25"; 219 reg = <0x20>; 220 }; 221 u74: ina226@40 { /* u74 */ 222 compatible = "ti,ina226"; 223 #io-channel-cells = <1>; 224 label = "ina226-u74"; 225 reg = <0x40>; 226 shunt-resistor = <1000>; 227 }; 228 u75: ina226@41 { /* u75 */ 229 compatible = "ti,ina226"; 230 #io-channel-cells = <1>; 231 label = "ina226-u75"; 232 reg = <0x41>; 233 shunt-resistor = <1000>; 234 }; 235 u78: ina226@42 { /* u78 */ 236 compatible = "ti,ina226"; 237 #io-channel-cells = <1>; 238 label = "ina226-u78"; 239 reg = <0x42>; 240 shunt-resistor = <5000>; 241 }; 242 u79: ina226@43 { /* u79 */ 243 compatible = "ti,ina226"; 244 #io-channel-cells = <1>; 245 label = "ina226-u79"; 246 reg = <0x43>; 247 shunt-resistor = <1000>; 248 }; 249 u82: ina226@44 { /* u82 */ 250 compatible = "ti,ina226"; 251 #io-channel-cells = <1>; 252 label = "ina226-u82"; 253 reg = <0x44>; 254 shunt-resistor = <1000>; 255 }; 256 u84: ina226@45 { /* u84 */ 257 compatible = "ti,ina226"; 258 #io-channel-cells = <1>; 259 label = "ina226-u84"; 260 reg = <0x45>; 261 shunt-resistor = <5000>; 262 }; 263 tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ 264 compatible = "ti,tps53681", "ti,tps53679"; 265 reg = <0xc0>; 266 }; 267 }; 268 i2c@3 { /* fmc1 via JA2G */ 269 #address-cells = <1>; 270 #size-cells = <0>; 271 reg = <3>; 272 eeprom_fmc1: eeprom@50 { /* on FMC */ 273 compatible = "atmel,24c04"; 274 reg = <0x50>; 275 }; 276 }; 277 i2c@4 { /* fmc2 via JA3G */ 278 #address-cells = <1>; 279 #size-cells = <0>; 280 reg = <4>; 281 eeprom_fmc2: eeprom@50 { /* on FMC */ 282 compatible = "atmel,24c04"; 283 reg = <0x50>; 284 }; 285 }; 286 i2c@5 { /* fmc3 via JA4G */ 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <5>; 290 eeprom_fmc3: eeprom@50 { /* on FMC */ 291 compatible = "atmel,24c04"; 292 reg = <0x50>; 293 }; 294 }; 295 i2c@6 { /* ddr dimm */ 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <7>; 299 }; 300 /* 7 unused */ 301 }; 302}; 303 304&usb0 { /* USB0 MIO52-63 */ 305 status = "okay"; 306 xlnx,usb-polarity = <0>; 307 xlnx,usb-reset-mode = <0>; 308}; 309 310&dwc3_0 { 311 status = "okay"; 312 dr_mode = "peripheral"; 313 maximum-speed = "high-speed"; 314}; 315