1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU111 4 * 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU111 RevA"; 21 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 mmc0 = &sdhci1; 28 nvmem0 = &eeprom; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &dcc; 32 spi0 = &qspi; 33 usb0 = &usb0; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 }; 40 41 memory@0 { 42 device_type = "memory"; 43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 44 /* Another 4GB connected to PL */ 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 autorepeat; 50 sw19 { 51 label = "sw19"; 52 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 53 linux,code = <KEY_DOWN>; 54 wakeup-source; 55 autorepeat; 56 }; 57 }; 58 59 leds { 60 compatible = "gpio-leds"; 61 heartbeat-led { 62 label = "heartbeat"; 63 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 68 ina226-u67 { 69 compatible = "iio-hwmon"; 70 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; 71 }; 72 ina226-u59 { 73 compatible = "iio-hwmon"; 74 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; 75 }; 76 ina226-u61 { 77 compatible = "iio-hwmon"; 78 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; 79 }; 80 ina226-u60 { 81 compatible = "iio-hwmon"; 82 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; 83 }; 84 ina226-u64 { 85 compatible = "iio-hwmon"; 86 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; 87 }; 88 ina226-u69 { 89 compatible = "iio-hwmon"; 90 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; 91 }; 92 ina226-u66 { 93 compatible = "iio-hwmon"; 94 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; 95 }; 96 ina226-u65 { 97 compatible = "iio-hwmon"; 98 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 99 }; 100 ina226-u63 { 101 compatible = "iio-hwmon"; 102 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; 103 }; 104 ina226-u3 { 105 compatible = "iio-hwmon"; 106 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; 107 }; 108 ina226-u71 { 109 compatible = "iio-hwmon"; 110 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; 111 }; 112 ina226-u77 { 113 compatible = "iio-hwmon"; 114 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 115 }; 116 ina226-u73 { 117 compatible = "iio-hwmon"; 118 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; 119 }; 120 ina226-u79 { 121 compatible = "iio-hwmon"; 122 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 123 }; 124 125 /* 48MHz reference crystal */ 126 ref48: ref48M { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <48000000>; 130 }; 131}; 132 133&dcc { 134 status = "okay"; 135}; 136 137&fpd_dma_chan1 { 138 status = "okay"; 139}; 140 141&fpd_dma_chan2 { 142 status = "okay"; 143}; 144 145&fpd_dma_chan3 { 146 status = "okay"; 147}; 148 149&fpd_dma_chan4 { 150 status = "okay"; 151}; 152 153&fpd_dma_chan5 { 154 status = "okay"; 155}; 156 157&fpd_dma_chan6 { 158 status = "okay"; 159}; 160 161&fpd_dma_chan7 { 162 status = "okay"; 163}; 164 165&fpd_dma_chan8 { 166 status = "okay"; 167}; 168 169&gem3 { 170 status = "okay"; 171 phy-handle = <&phy0>; 172 phy-mode = "rgmii-id"; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_gem3_default>; 175 phy0: ethernet-phy@c { 176 reg = <0xc>; 177 ti,rx-internal-delay = <0x8>; 178 ti,tx-internal-delay = <0xa>; 179 ti,fifo-depth = <0x1>; 180 ti,dp83867-rxctrl-strap-quirk; 181 }; 182}; 183 184&gpio { 185 status = "okay"; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_gpio_default>; 188}; 189 190&gpu { 191 status = "okay"; 192}; 193 194&i2c0 { 195 status = "okay"; 196 clock-frequency = <400000>; 197 pinctrl-names = "default", "gpio"; 198 pinctrl-0 = <&pinctrl_i2c0_default>; 199 pinctrl-1 = <&pinctrl_i2c0_gpio>; 200 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 201 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 202 203 tca6416_u22: gpio@20 { 204 compatible = "ti,tca6416"; 205 reg = <0x20>; 206 gpio-controller; /* interrupt not connected */ 207 #gpio-cells = <2>; 208 /* 209 * IRQ not connected 210 * Lines: 211 * 0 - MAX6643_OT_B 212 * 1 - MAX6643_FANFAIL_B 213 * 2 - MIO26_PMU_INPUT_LS 214 * 4 - SFP_SI5382_INT_ALM 215 * 5 - IIC_MUX_RESET_B 216 * 6 - GEM3_EXP_RESET_B 217 * 10 - FMCP_HSPC_PRSNT_M2C_B 218 * 11 - CLK_SPI_MUX_SEL0 219 * 12 - CLK_SPI_MUX_SEL1 220 * 16 - IRPS5401_ALERT_B 221 * 17 - INA226_PMBUS_ALERT 222 * 3, 7, 13-15 - not connected 223 */ 224 }; 225 226 i2c-mux@75 { /* u23 */ 227 compatible = "nxp,pca9544"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0x75>; 231 i2c@0 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0>; 235 /* PS_PMBUS */ 236 /* PMBUS_ALERT done via pca9544 */ 237 u67: ina226@40 { /* u67 */ 238 compatible = "ti,ina226"; 239 #io-channel-cells = <1>; 240 label = "ina226-u67"; 241 reg = <0x40>; 242 shunt-resistor = <2000>; 243 }; 244 u59: ina226@41 { /* u59 */ 245 compatible = "ti,ina226"; 246 #io-channel-cells = <1>; 247 label = "ina226-u59"; 248 reg = <0x41>; 249 shunt-resistor = <5000>; 250 }; 251 u61: ina226@42 { /* u61 */ 252 compatible = "ti,ina226"; 253 #io-channel-cells = <1>; 254 label = "ina226-u61"; 255 reg = <0x42>; 256 shunt-resistor = <5000>; 257 }; 258 u60: ina226@43 { /* u60 */ 259 compatible = "ti,ina226"; 260 #io-channel-cells = <1>; 261 label = "ina226-u60"; 262 reg = <0x43>; 263 shunt-resistor = <5000>; 264 }; 265 u64: ina226@45 { /* u64 */ 266 compatible = "ti,ina226"; 267 #io-channel-cells = <1>; 268 label = "ina226-u64"; 269 reg = <0x45>; 270 shunt-resistor = <5000>; 271 }; 272 u69: ina226@46 { /* u69 */ 273 compatible = "ti,ina226"; 274 #io-channel-cells = <1>; 275 label = "ina226-u69"; 276 reg = <0x46>; 277 shunt-resistor = <2000>; 278 }; 279 u66: ina226@47 { /* u66 */ 280 compatible = "ti,ina226"; 281 #io-channel-cells = <1>; 282 label = "ina226-u66"; 283 reg = <0x47>; 284 shunt-resistor = <5000>; 285 }; 286 u65: ina226@48 { /* u65 */ 287 compatible = "ti,ina226"; 288 #io-channel-cells = <1>; 289 label = "ina226-u65"; 290 reg = <0x48>; 291 shunt-resistor = <5000>; 292 }; 293 u63: ina226@49 { /* u63 */ 294 compatible = "ti,ina226"; 295 #io-channel-cells = <1>; 296 label = "ina226-u63"; 297 reg = <0x49>; 298 shunt-resistor = <5000>; 299 }; 300 u3: ina226@4a { /* u3 */ 301 compatible = "ti,ina226"; 302 #io-channel-cells = <1>; 303 label = "ina226-u3"; 304 reg = <0x4a>; 305 shunt-resistor = <5000>; 306 }; 307 u71: ina226@4b { /* u71 */ 308 compatible = "ti,ina226"; 309 #io-channel-cells = <1>; 310 label = "ina226-u71"; 311 reg = <0x4b>; 312 shunt-resistor = <5000>; 313 }; 314 u77: ina226@4c { /* u77 */ 315 compatible = "ti,ina226"; 316 #io-channel-cells = <1>; 317 label = "ina226-u77"; 318 reg = <0x4c>; 319 shunt-resistor = <5000>; 320 }; 321 u73: ina226@4d { /* u73 */ 322 compatible = "ti,ina226"; 323 #io-channel-cells = <1>; 324 label = "ina226-u73"; 325 reg = <0x4d>; 326 shunt-resistor = <5000>; 327 }; 328 u79: ina226@4e { /* u79 */ 329 compatible = "ti,ina226"; 330 #io-channel-cells = <1>; 331 label = "ina226-u79"; 332 reg = <0x4e>; 333 shunt-resistor = <5000>; 334 }; 335 }; 336 i2c@1 { 337 #address-cells = <1>; 338 #size-cells = <0>; 339 reg = <1>; 340 /* NC */ 341 }; 342 i2c@2 { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 reg = <2>; 346 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ 347 compatible = "infineon,irps5401"; 348 reg = <0x43>; 349 }; 350 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ 351 compatible = "infineon,irps5401"; 352 reg = <0x44>; 353 }; 354 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ 355 compatible = "infineon,irps5401"; 356 reg = <0x45>; 357 }; 358 /* u68 IR38064 +0 */ 359 /* u70 IR38060 +1 */ 360 /* u74 IR38060 +2 */ 361 /* u75 IR38060 +6 */ 362 /* J19 header too */ 363 364 }; 365 i2c@3 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <3>; 369 /* SYSMON */ 370 }; 371 }; 372}; 373 374&i2c1 { 375 status = "okay"; 376 clock-frequency = <400000>; 377 pinctrl-names = "default", "gpio"; 378 pinctrl-0 = <&pinctrl_i2c1_default>; 379 pinctrl-1 = <&pinctrl_i2c1_gpio>; 380 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 381 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 382 383 i2c-mux@74 { /* u26 */ 384 compatible = "nxp,pca9548"; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 reg = <0x74>; 388 i2c@0 { 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0>; 392 /* 393 * IIC_EEPROM 1kB memory which uses 256B blocks 394 * where every block has different address. 395 * 0 - 256B address 0x54 396 * 256B - 512B address 0x55 397 * 512B - 768B address 0x56 398 * 768B - 1024B address 0x57 399 */ 400 eeprom: eeprom@54 { /* u88 */ 401 compatible = "atmel,24c08"; 402 reg = <0x54>; 403 }; 404 }; 405 i2c@1 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 reg = <1>; 409 si5341: clock-generator@36 { /* SI5341 - u46 */ 410 compatible = "silabs,si5341"; 411 reg = <0x36>; 412 #clock-cells = <2>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&ref48>; 416 clock-names = "xtal"; 417 clock-output-names = "si5341"; 418 419 si5341_0: out@0 { 420 /* refclk0 for PS-GT, used for DP */ 421 reg = <0>; 422 always-on; 423 }; 424 si5341_2: out@2 { 425 /* refclk2 for PS-GT, used for USB3 */ 426 reg = <2>; 427 always-on; 428 }; 429 si5341_3: out@3 { 430 /* refclk3 for PS-GT, used for SATA */ 431 reg = <3>; 432 always-on; 433 }; 434 si5341_5: out@5 { 435 /* refclk5 PL CLK100 */ 436 reg = <5>; 437 always-on; 438 }; 439 si5341_6: out@6 { 440 /* refclk6 PL CLK125 */ 441 reg = <6>; 442 always-on; 443 }; 444 si5341_9: out@9 { 445 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 446 reg = <9>; 447 always-on; 448 }; 449 }; 450 }; 451 i2c@2 { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <2>; 455 si570_1: clock-generator@5d { /* USER SI570 - u47 */ 456 #clock-cells = <0>; 457 compatible = "silabs,si570"; 458 reg = <0x5d>; 459 temperature-stability = <50>; 460 factory-fout = <300000000>; 461 clock-frequency = <300000000>; 462 clock-output-names = "si570_user"; 463 }; 464 }; 465 i2c@3 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <3>; 469 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ 470 #clock-cells = <0>; 471 compatible = "silabs,si570"; 472 reg = <0x5d>; 473 temperature-stability = <50>; 474 factory-fout = <156250000>; 475 clock-frequency = <156250000>; 476 clock-output-names = "si570_mgt"; 477 }; 478 }; 479 i2c@4 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 reg = <4>; 483 /* SI5382 - u48 */ 484 }; 485 i2c@5 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 reg = <5>; 489 sc18is603@2f { /* sc18is602 - u93 */ 490 compatible = "nxp,sc18is603"; 491 reg = <0x2f>; 492 /* 4 gpios for CS not handled by driver */ 493 /* 494 * USB2ANY cable or 495 * LMK04208 - u90 or 496 * LMX2594 - u102 or 497 * LMX2594 - u103 or 498 * LMX2594 - u104 499 */ 500 }; 501 }; 502 i2c@6 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <6>; 506 /* FMC connector */ 507 }; 508 /* 7 NC */ 509 }; 510 511 i2c-mux@75 { 512 compatible = "nxp,pca9548"; /* u27 */ 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0x75>; 516 517 i2c@0 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0>; 521 /* FMCP_HSPC_IIC */ 522 }; 523 i2c@1 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <1>; 527 /* NC */ 528 }; 529 i2c@2 { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <2>; 533 /* SYSMON */ 534 }; 535 i2c@3 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 reg = <3>; 539 /* DDR4 SODIMM */ 540 }; 541 i2c@4 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <4>; 545 /* SFP3 */ 546 }; 547 i2c@5 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <5>; 551 /* SFP2 */ 552 }; 553 i2c@6 { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 reg = <6>; 557 /* SFP1 */ 558 }; 559 i2c@7 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <7>; 563 /* SFP0 */ 564 }; 565 }; 566}; 567 568&pinctrl0 { 569 status = "okay"; 570 pinctrl_i2c0_default: i2c0-default { 571 mux { 572 groups = "i2c0_3_grp"; 573 function = "i2c0"; 574 }; 575 576 conf { 577 groups = "i2c0_3_grp"; 578 bias-pull-up; 579 slew-rate = <SLEW_RATE_SLOW>; 580 power-source = <IO_STANDARD_LVCMOS18>; 581 }; 582 }; 583 584 pinctrl_i2c0_gpio: i2c0-gpio { 585 mux { 586 groups = "gpio0_14_grp", "gpio0_15_grp"; 587 function = "gpio0"; 588 }; 589 590 conf { 591 groups = "gpio0_14_grp", "gpio0_15_grp"; 592 slew-rate = <SLEW_RATE_SLOW>; 593 power-source = <IO_STANDARD_LVCMOS18>; 594 }; 595 }; 596 597 pinctrl_i2c1_default: i2c1-default { 598 mux { 599 groups = "i2c1_4_grp"; 600 function = "i2c1"; 601 }; 602 603 conf { 604 groups = "i2c1_4_grp"; 605 bias-pull-up; 606 slew-rate = <SLEW_RATE_SLOW>; 607 power-source = <IO_STANDARD_LVCMOS18>; 608 }; 609 }; 610 611 pinctrl_i2c1_gpio: i2c1-gpio { 612 mux { 613 groups = "gpio0_16_grp", "gpio0_17_grp"; 614 function = "gpio0"; 615 }; 616 617 conf { 618 groups = "gpio0_16_grp", "gpio0_17_grp"; 619 slew-rate = <SLEW_RATE_SLOW>; 620 power-source = <IO_STANDARD_LVCMOS18>; 621 }; 622 }; 623 624 pinctrl_uart0_default: uart0-default { 625 mux { 626 groups = "uart0_4_grp"; 627 function = "uart0"; 628 }; 629 630 conf { 631 groups = "uart0_4_grp"; 632 slew-rate = <SLEW_RATE_SLOW>; 633 power-source = <IO_STANDARD_LVCMOS18>; 634 }; 635 636 conf-rx { 637 pins = "MIO18"; 638 bias-high-impedance; 639 }; 640 641 conf-tx { 642 pins = "MIO19"; 643 bias-disable; 644 }; 645 }; 646 647 pinctrl_usb0_default: usb0-default { 648 mux { 649 groups = "usb0_0_grp"; 650 function = "usb0"; 651 }; 652 653 conf { 654 groups = "usb0_0_grp"; 655 slew-rate = <SLEW_RATE_SLOW>; 656 power-source = <IO_STANDARD_LVCMOS18>; 657 }; 658 659 conf-rx { 660 pins = "MIO52", "MIO53", "MIO55"; 661 bias-high-impedance; 662 }; 663 664 conf-tx { 665 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 666 "MIO60", "MIO61", "MIO62", "MIO63"; 667 bias-disable; 668 }; 669 }; 670 671 pinctrl_gem3_default: gem3-default { 672 mux { 673 function = "ethernet3"; 674 groups = "ethernet3_0_grp"; 675 }; 676 677 conf { 678 groups = "ethernet3_0_grp"; 679 slew-rate = <SLEW_RATE_SLOW>; 680 power-source = <IO_STANDARD_LVCMOS18>; 681 }; 682 683 conf-rx { 684 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 685 "MIO75"; 686 bias-high-impedance; 687 low-power-disable; 688 }; 689 690 conf-tx { 691 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 692 "MIO69"; 693 bias-disable; 694 low-power-enable; 695 }; 696 697 mux-mdio { 698 function = "mdio3"; 699 groups = "mdio3_0_grp"; 700 }; 701 702 conf-mdio { 703 groups = "mdio3_0_grp"; 704 slew-rate = <SLEW_RATE_SLOW>; 705 power-source = <IO_STANDARD_LVCMOS18>; 706 bias-disable; 707 }; 708 }; 709 710 pinctrl_sdhci1_default: sdhci1-default { 711 mux { 712 groups = "sdio1_0_grp"; 713 function = "sdio1"; 714 }; 715 716 conf { 717 groups = "sdio1_0_grp"; 718 slew-rate = <SLEW_RATE_SLOW>; 719 power-source = <IO_STANDARD_LVCMOS18>; 720 bias-disable; 721 }; 722 723 mux-cd { 724 groups = "sdio1_cd_0_grp"; 725 function = "sdio1_cd"; 726 }; 727 728 conf-cd { 729 groups = "sdio1_cd_0_grp"; 730 bias-high-impedance; 731 bias-pull-up; 732 slew-rate = <SLEW_RATE_SLOW>; 733 power-source = <IO_STANDARD_LVCMOS18>; 734 }; 735 }; 736 737 pinctrl_gpio_default: gpio-default { 738 mux { 739 function = "gpio0"; 740 groups = "gpio0_22_grp", "gpio0_23_grp"; 741 }; 742 743 conf { 744 groups = "gpio0_22_grp", "gpio0_23_grp"; 745 slew-rate = <SLEW_RATE_SLOW>; 746 power-source = <IO_STANDARD_LVCMOS18>; 747 }; 748 749 mux-msp { 750 function = "gpio0"; 751 groups = "gpio0_13_grp", "gpio0_38_grp"; 752 }; 753 754 conf-msp { 755 groups = "gpio0_13_grp", "gpio0_38_grp"; 756 slew-rate = <SLEW_RATE_SLOW>; 757 power-source = <IO_STANDARD_LVCMOS18>; 758 }; 759 760 conf-pull-up { 761 pins = "MIO22"; 762 bias-pull-up; 763 }; 764 765 conf-pull-none { 766 pins = "MIO13", "MIO23", "MIO38"; 767 bias-disable; 768 }; 769 }; 770}; 771 772&psgtr { 773 status = "okay"; 774 /* nc, dp, usb3, sata */ 775 clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; 776 clock-names = "ref1", "ref2", "ref3"; 777}; 778 779&qspi { 780 status = "okay"; 781 is-dual = <1>; 782 flash@0 { 783 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 784 #address-cells = <1>; 785 #size-cells = <1>; 786 reg = <0x0>; 787 spi-tx-bus-width = <1>; 788 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 789 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 790 partition@0 { /* for testing purpose */ 791 label = "qspi-fsbl-uboot"; 792 reg = <0x0 0x100000>; 793 }; 794 partition@100000 { /* for testing purpose */ 795 label = "qspi-linux"; 796 reg = <0x100000 0x500000>; 797 }; 798 partition@600000 { /* for testing purpose */ 799 label = "qspi-device-tree"; 800 reg = <0x600000 0x20000>; 801 }; 802 partition@620000 { /* for testing purpose */ 803 label = "qspi-rootfs"; 804 reg = <0x620000 0x5E0000>; 805 }; 806 }; 807}; 808 809&rtc { 810 status = "okay"; 811}; 812 813&sata { 814 status = "okay"; 815 /* SATA OOB timing settings */ 816 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 817 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 818 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 819 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 820 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 821 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 822 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 823 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 824 phy-names = "sata-phy"; 825 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 826}; 827 828/* SD1 with level shifter */ 829&sdhci1 { 830 status = "okay"; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&pinctrl_sdhci1_default>; 833 disable-wp; 834 /* 835 * This property should be removed for supporting UHS mode 836 */ 837 no-1-8-v; 838 xlnx,mio-bank = <1>; 839}; 840 841&uart0 { 842 status = "okay"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&pinctrl_uart0_default>; 845}; 846 847/* ULPI SMSC USB3320 */ 848&usb0 { 849 status = "okay"; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&pinctrl_usb0_default>; 852 phy-names = "usb3-phy"; 853 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 854}; 855 856&dwc3_0 { 857 status = "okay"; 858 dr_mode = "host"; 859 snps,usb3_lpm_capable; 860 maximum-speed = "super-speed"; 861}; 862 863&zynqmp_dpdma { 864 status = "okay"; 865}; 866 867&zynqmp_dpsub { 868 status = "okay"; 869 phy-names = "dp-phy0", "dp-phy1"; 870 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 871 <&psgtr 0 PHY_TYPE_DP 1 1>; 872}; 873