1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7 #ifndef __CSRS_RVU_H__
8 #define __CSRS_RVU_H__
9
10 /**
11 * @file
12 *
13 * Configuration and status register (CSR) address and type definitions for
14 * RVU.
15 *
16 * This file is auto generated. Do not edit.
17 *
18 */
19
20 /**
21 * Enumeration rvu_af_int_vec_e
22 *
23 * RVU Admin Function Interrupt Vector Enumeration Enumerates the MSI-X
24 * interrupt vectors. Internal: RVU maintains the state of these vectors
25 * internally, and generates GIB messages for it without accessing the
26 * MSI-X table region in LLC/DRAM.
27 */
28 #define RVU_AF_INT_VEC_E_GEN (3)
29 #define RVU_AF_INT_VEC_E_MBOX (4)
30 #define RVU_AF_INT_VEC_E_PFFLR (1)
31 #define RVU_AF_INT_VEC_E_PFME (2)
32 #define RVU_AF_INT_VEC_E_POISON (0)
33
34 /**
35 * Enumeration rvu_bar_e
36 *
37 * RVU Base Address Register Enumeration Enumerates the base address
38 * registers. Internal: For documentation only.
39 */
40 #define RVU_BAR_E_RVU_PFX_BAR0(a) (0x840000000000ll + 0x1000000000ll * (a))
41 #define RVU_BAR_E_RVU_PFX_BAR0_SIZE 0x10000000ull
42 #define RVU_BAR_E_RVU_PFX_FUNCX_BAR2(a, b) \
43 (0x840200000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b))
44 #define RVU_BAR_E_RVU_PFX_FUNCX_BAR2_SIZE 0x100000ull
45 #define RVU_BAR_E_RVU_PFX_FUNCX_BAR4(a, b) \
46 (0x840400000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b))
47 #define RVU_BAR_E_RVU_PFX_FUNCX_BAR4_SIZE 0x10000ull
48
49 /**
50 * Enumeration rvu_block_addr_e
51 *
52 * RVU Block Address Enumeration Enumerates addressing of RVU resource
53 * blocks within each RVU BAR, i.e. values of RVU_FUNC_ADDR_S[BLOCK] and
54 * RVU_AF_ADDR_S[BLOCK]. CNXXXX may not implement all enumerated blocks.
55 * Software can read RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[IMP] to discover
56 * which blocks are implemented and enabled.
57 */
58 #define RVU_BLOCK_ADDR_E_CPTX(a) (0xa + (a))
59 #define RVU_BLOCK_ADDR_E_LMT (1)
60 #define RVU_BLOCK_ADDR_E_NDCX(a) (0xc + (a))
61 #define RVU_BLOCK_ADDR_E_NIXX(a) (4 + (a))
62 #define RVU_BLOCK_ADDR_E_NPA (3)
63 #define RVU_BLOCK_ADDR_E_NPC (6)
64 #define RVU_BLOCK_ADDR_E_RX(a) (0 + (a))
65 #define RVU_BLOCK_ADDR_E_REEX(a) (0x14 + (a))
66 #define RVU_BLOCK_ADDR_E_RVUM (0)
67 #define RVU_BLOCK_ADDR_E_SSO (7)
68 #define RVU_BLOCK_ADDR_E_SSOW (8)
69 #define RVU_BLOCK_ADDR_E_TIM (9)
70
71 /**
72 * Enumeration rvu_block_type_e
73 *
74 * RVU Block Type Enumeration Enumerates values of
75 * RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[BTYPE].
76 */
77 #define RVU_BLOCK_TYPE_E_CPT (9)
78 #define RVU_BLOCK_TYPE_E_DDF (0xb)
79 #define RVU_BLOCK_TYPE_E_LMT (2)
80 #define RVU_BLOCK_TYPE_E_NDC (0xa)
81 #define RVU_BLOCK_TYPE_E_NIX (3)
82 #define RVU_BLOCK_TYPE_E_NPA (4)
83 #define RVU_BLOCK_TYPE_E_NPC (5)
84 #define RVU_BLOCK_TYPE_E_RAD (0xd)
85 #define RVU_BLOCK_TYPE_E_REE (0xe)
86 #define RVU_BLOCK_TYPE_E_RVUM (0)
87 #define RVU_BLOCK_TYPE_E_SSO (6)
88 #define RVU_BLOCK_TYPE_E_SSOW (7)
89 #define RVU_BLOCK_TYPE_E_TIM (8)
90 #define RVU_BLOCK_TYPE_E_ZIP (0xc)
91
92 /**
93 * Enumeration rvu_bus_lf_e
94 *
95 * INTERNAL: RVU Bus LF Range Enumeration Enumerates the LF range for
96 * the RVU bus. Internal: This is an enum used in csr3 virtual equations.
97 */
98 #define RVU_BUS_LF_E_RVU_BUS_LFX(a) (0 + 0x2000000 * (a))
99
100 /**
101 * Enumeration rvu_bus_lf_slot_e
102 *
103 * INTERNAL: RVU Bus LF Slot Range Enumeration Enumerates the LF and
104 * Slot range for the RVU bus. Internal: This is an enum used in csr3
105 * virtual equations.
106 */
107 #define RVU_BUS_LF_SLOT_E_RVU_BUS_LFX_SLOTX(a, b) \
108 (0 + 0x2000000 * (a) + 0x1000 * (b))
109
110 /**
111 * Enumeration rvu_bus_pf_e
112 *
113 * INTERNAL: RVU Bus PF Range Enumeration Enumerates the PF range for
114 * the RVU bus. Internal: This is an enum used in csr3 virtual equations.
115 */
116 #define RVU_BUS_PF_E_RVU_BUS_PFX(a) (0ll + 0x1000000000ll * (a))
117
118 /**
119 * Enumeration rvu_bus_pfvf_e
120 *
121 * INTERNAL: RVU Bus PFVF Range Enumeration Enumerates the PF and VF
122 * ranges for the RVU bus. Internal: This is an enum used in csr3 virtual
123 * equations.
124 */
125 #define RVU_BUS_PFVF_E_RVU_BUS_PFX(a) (0 + 0x2000000 * (a))
126 #define RVU_BUS_PFVF_E_RVU_BUS_VFX(a) (0 + 0x2000000 * (a))
127
128 /**
129 * Enumeration rvu_busbar_e
130 *
131 * INTERNAL: RVU Bus Base Address Region Enumeration Enumerates the base
132 * address region for the RVU bus. Internal: This is an enum used in csr3
133 * virtual equations.
134 */
135 #define RVU_BUSBAR_E_RVU_BUSBAR0 (0)
136 #define RVU_BUSBAR_E_RVU_BUSBAR2 (0x200000000ll)
137
138 /**
139 * Enumeration rvu_busdid_e
140 *
141 * INTERNAL: RVU Bus DID Enumeration Enumerates the DID offset for the
142 * RVU bus. Internal: This is an enum used in csr3 virtual equations.
143 */
144 #define RVU_BUSDID_E_RVU_BUSDID (0x840000000000ll)
145
146 /**
147 * Enumeration rvu_pf_int_vec_e
148 *
149 * RVU PF Interrupt Vector Enumeration Enumerates the MSI-X interrupt
150 * vectors.
151 */
152 #define RVU_PF_INT_VEC_E_AFPF_MBOX (6)
153 #define RVU_PF_INT_VEC_E_VFFLRX(a) (0 + (a))
154 #define RVU_PF_INT_VEC_E_VFMEX(a) (2 + (a))
155 #define RVU_PF_INT_VEC_E_VFPF_MBOXX(a) (4 + (a))
156
157 /**
158 * Enumeration rvu_vf_int_vec_e
159 *
160 * RVU VF Interrupt Vector Enumeration Enumerates the MSI-X interrupt
161 * vectors.
162 */
163 #define RVU_VF_INT_VEC_E_MBOX (0)
164
165 /**
166 * Structure rvu_af_addr_s
167 *
168 * RVU Admin Function Register Address Structure Address format for
169 * accessing shared Admin Function (AF) registers in RVU PF BAR0. These
170 * registers may be accessed by all RVU PFs whose
171 * RVU_PRIV_PF()_CFG[AF_ENA] bit is set.
172 */
173 union rvu_af_addr_s {
174 u64 u;
175 struct rvu_af_addr_s_s {
176 u64 addr : 28;
177 u64 block : 5;
178 u64 reserved_33_63 : 31;
179 } s;
180 /* struct rvu_af_addr_s_s cn; */
181 };
182
183 /**
184 * Structure rvu_func_addr_s
185 *
186 * RVU Function-unique Address Structure Address format for accessing
187 * function-unique registers in RVU PF/FUNC BAR2.
188 */
189 union rvu_func_addr_s {
190 u32 u;
191 struct rvu_func_addr_s_s {
192 u32 addr : 12;
193 u32 lf_slot : 8;
194 u32 block : 5;
195 u32 reserved_25_31 : 7;
196 } s;
197 /* struct rvu_func_addr_s_s cn; */
198 };
199
200 /**
201 * Structure rvu_msix_vec_s
202 *
203 * RVU MSI-X Vector Structure Format of entries in the RVU MSI-X table
204 * region in LLC/DRAM. See RVU_PRIV_PF()_MSIX_CFG.
205 */
206 union rvu_msix_vec_s {
207 u64 u[2];
208 struct rvu_msix_vec_s_s {
209 u64 addr : 64;
210 u64 data : 32;
211 u64 mask : 1;
212 u64 pend : 1;
213 u64 reserved_98_127 : 30;
214 } s;
215 /* struct rvu_msix_vec_s_s cn; */
216 };
217
218 /**
219 * Structure rvu_pf_func_s
220 *
221 * RVU PF Function Identification Structure Identifies an RVU PF/VF, and
222 * format of *_PRIV_LF()_CFG[PF_FUNC] in RVU resource blocks, e.g.
223 * NPA_PRIV_LF()_CFG[PF_FUNC]. Internal: Also used for PF/VF
224 * identification on inter-coprocessor hardware interfaces (NPA, SSO,
225 * CPT, ...).
226 */
227 union rvu_pf_func_s {
228 u32 u;
229 struct rvu_pf_func_s_s {
230 u32 func : 10;
231 u32 pf : 6;
232 u32 reserved_16_31 : 16;
233 } s;
234 /* struct rvu_pf_func_s_s cn; */
235 };
236
237 /**
238 * Register (RVU_PF_BAR0) rvu_af_afpf#_mbox#
239 *
240 * RVU Admin Function AF/PF Mailbox Registers
241 */
242 union rvu_af_afpfx_mboxx {
243 u64 u;
244 struct rvu_af_afpfx_mboxx_s {
245 u64 data : 64;
246 } s;
247 /* struct rvu_af_afpfx_mboxx_s cn; */
248 };
249
250 static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b)
251 __attribute__ ((pure, always_inline));
RVU_AF_AFPFX_MBOXX(u64 a,u64 b)252 static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b)
253 {
254 return 0x2000 + 0x10 * a + 8 * b;
255 }
256
257 /**
258 * Register (RVU_PF_BAR0) rvu_af_bar2_alias#
259 *
260 * INTERNAL: RVU Admin Function BAR2 Alias Registers These registers
261 * alias to the RVU BAR2 registers for the PF and function selected by
262 * RVU_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for
263 * bug33464.
264 */
265 union rvu_af_bar2_aliasx {
266 u64 u;
267 struct rvu_af_bar2_aliasx_s {
268 u64 data : 64;
269 } s;
270 /* struct rvu_af_bar2_aliasx_s cn; */
271 };
272
273 static inline u64 RVU_AF_BAR2_ALIASX(u64 a)
274 __attribute__ ((pure, always_inline));
RVU_AF_BAR2_ALIASX(u64 a)275 static inline u64 RVU_AF_BAR2_ALIASX(u64 a)
276 {
277 return 0x9100000 + 8 * a;
278 }
279
280 /**
281 * Register (RVU_PF_BAR0) rvu_af_bar2_sel
282 *
283 * INTERNAL: RVU Admin Function BAR2 Select Register This register
284 * configures BAR2 accesses from the RVU_AF_BAR2_ALIAS() registers in
285 * BAR0. Internal: Not implemented. Placeholder for bug33464.
286 */
287 union rvu_af_bar2_sel {
288 u64 u;
289 struct rvu_af_bar2_sel_s {
290 u64 alias_pf_func : 16;
291 u64 alias_ena : 1;
292 u64 reserved_17_63 : 47;
293 } s;
294 /* struct rvu_af_bar2_sel_s cn; */
295 };
296
297 static inline u64 RVU_AF_BAR2_SEL(void)
298 __attribute__ ((pure, always_inline));
RVU_AF_BAR2_SEL(void)299 static inline u64 RVU_AF_BAR2_SEL(void)
300 {
301 return 0x9000000;
302 }
303
304 /**
305 * Register (RVU_PF_BAR0) rvu_af_blk_rst
306 *
307 * RVU Master Admin Function Block Reset Register
308 */
309 union rvu_af_blk_rst {
310 u64 u;
311 struct rvu_af_blk_rst_s {
312 u64 rst : 1;
313 u64 reserved_1_62 : 62;
314 u64 busy : 1;
315 } s;
316 /* struct rvu_af_blk_rst_s cn; */
317 };
318
319 static inline u64 RVU_AF_BLK_RST(void)
320 __attribute__ ((pure, always_inline));
RVU_AF_BLK_RST(void)321 static inline u64 RVU_AF_BLK_RST(void)
322 {
323 return 0x30;
324 }
325
326 /**
327 * Register (RVU_PF_BAR0) rvu_af_bp_test
328 *
329 * INTERNAL: RVUM Backpressure Test Registers
330 */
331 union rvu_af_bp_test {
332 u64 u;
333 struct rvu_af_bp_test_s {
334 u64 lfsr_freq : 12;
335 u64 reserved_12_15 : 4;
336 u64 bp_cfg : 16;
337 u64 enable : 8;
338 u64 reserved_40_63 : 24;
339 } s;
340 /* struct rvu_af_bp_test_s cn; */
341 };
342
343 static inline u64 RVU_AF_BP_TEST(void)
344 __attribute__ ((pure, always_inline));
RVU_AF_BP_TEST(void)345 static inline u64 RVU_AF_BP_TEST(void)
346 {
347 return 0x4000;
348 }
349
350 /**
351 * Register (RVU_PF_BAR0) rvu_af_eco
352 *
353 * INTERNAL: RVU Admin Function ECO Register
354 */
355 union rvu_af_eco {
356 u64 u;
357 struct rvu_af_eco_s {
358 u64 eco_rw : 32;
359 u64 reserved_32_63 : 32;
360 } s;
361 /* struct rvu_af_eco_s cn; */
362 };
363
364 static inline u64 RVU_AF_ECO(void)
365 __attribute__ ((pure, always_inline));
RVU_AF_ECO(void)366 static inline u64 RVU_AF_ECO(void)
367 {
368 return 0x20;
369 }
370
371 /**
372 * Register (RVU_PF_BAR0) rvu_af_gen_int
373 *
374 * RVU Admin Function General Interrupt Register This register contains
375 * General interrupt summary bits.
376 */
377 union rvu_af_gen_int {
378 u64 u;
379 struct rvu_af_gen_int_s {
380 u64 unmapped : 1;
381 u64 msix_fault : 1;
382 u64 reserved_2_63 : 62;
383 } s;
384 /* struct rvu_af_gen_int_s cn; */
385 };
386
387 static inline u64 RVU_AF_GEN_INT(void)
388 __attribute__ ((pure, always_inline));
RVU_AF_GEN_INT(void)389 static inline u64 RVU_AF_GEN_INT(void)
390 {
391 return 0x120;
392 }
393
394 /**
395 * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1c
396 *
397 * RVU Admin Function General Interrupt Enable Clear Register This
398 * register clears interrupt enable bits.
399 */
400 union rvu_af_gen_int_ena_w1c {
401 u64 u;
402 struct rvu_af_gen_int_ena_w1c_s {
403 u64 unmapped : 1;
404 u64 msix_fault : 1;
405 u64 reserved_2_63 : 62;
406 } s;
407 /* struct rvu_af_gen_int_ena_w1c_s cn; */
408 };
409
410 static inline u64 RVU_AF_GEN_INT_ENA_W1C(void)
411 __attribute__ ((pure, always_inline));
RVU_AF_GEN_INT_ENA_W1C(void)412 static inline u64 RVU_AF_GEN_INT_ENA_W1C(void)
413 {
414 return 0x138;
415 }
416
417 /**
418 * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1s
419 *
420 * RVU Admin Function General Interrupt Enable Set Register This register
421 * sets interrupt enable bits.
422 */
423 union rvu_af_gen_int_ena_w1s {
424 u64 u;
425 struct rvu_af_gen_int_ena_w1s_s {
426 u64 unmapped : 1;
427 u64 msix_fault : 1;
428 u64 reserved_2_63 : 62;
429 } s;
430 /* struct rvu_af_gen_int_ena_w1s_s cn; */
431 };
432
433 static inline u64 RVU_AF_GEN_INT_ENA_W1S(void)
434 __attribute__ ((pure, always_inline));
RVU_AF_GEN_INT_ENA_W1S(void)435 static inline u64 RVU_AF_GEN_INT_ENA_W1S(void)
436 {
437 return 0x130;
438 }
439
440 /**
441 * Register (RVU_PF_BAR0) rvu_af_gen_int_w1s
442 *
443 * RVU Admin Function General Interrupt Set Register This register sets
444 * interrupt bits.
445 */
446 union rvu_af_gen_int_w1s {
447 u64 u;
448 struct rvu_af_gen_int_w1s_s {
449 u64 unmapped : 1;
450 u64 msix_fault : 1;
451 u64 reserved_2_63 : 62;
452 } s;
453 /* struct rvu_af_gen_int_w1s_s cn; */
454 };
455
456 static inline u64 RVU_AF_GEN_INT_W1S(void)
457 __attribute__ ((pure, always_inline));
RVU_AF_GEN_INT_W1S(void)458 static inline u64 RVU_AF_GEN_INT_W1S(void)
459 {
460 return 0x128;
461 }
462
463 /**
464 * Register (RVU_PF_BAR0) rvu_af_hwvf_rst
465 *
466 * RVU Admin Function Hardware VF Reset Register
467 */
468 union rvu_af_hwvf_rst {
469 u64 u;
470 struct rvu_af_hwvf_rst_s {
471 u64 hwvf : 8;
472 u64 reserved_8_11 : 4;
473 u64 exec : 1;
474 u64 reserved_13_63 : 51;
475 } s;
476 /* struct rvu_af_hwvf_rst_s cn; */
477 };
478
479 static inline u64 RVU_AF_HWVF_RST(void)
480 __attribute__ ((pure, always_inline));
RVU_AF_HWVF_RST(void)481 static inline u64 RVU_AF_HWVF_RST(void)
482 {
483 return 0x2850;
484 }
485
486 /**
487 * Register (RVU_PF_BAR0) rvu_af_msixtr_base
488 *
489 * RVU Admin Function MSI-X Table Region Base-Address Register
490 */
491 union rvu_af_msixtr_base {
492 u64 u;
493 struct rvu_af_msixtr_base_s {
494 u64 reserved_0_6 : 7;
495 u64 addr : 46;
496 u64 reserved_53_63 : 11;
497 } s;
498 /* struct rvu_af_msixtr_base_s cn; */
499 };
500
501 static inline u64 RVU_AF_MSIXTR_BASE(void)
502 __attribute__ ((pure, always_inline));
RVU_AF_MSIXTR_BASE(void)503 static inline u64 RVU_AF_MSIXTR_BASE(void)
504 {
505 return 0x10;
506 }
507
508 /**
509 * Register (RVU_PF_BAR0) rvu_af_pf#_vf_bar4_addr
510 *
511 * RVU Admin Function PF/VF BAR4 Address Registers
512 */
513 union rvu_af_pfx_vf_bar4_addr {
514 u64 u;
515 struct rvu_af_pfx_vf_bar4_addr_s {
516 u64 reserved_0_15 : 16;
517 u64 addr : 48;
518 } s;
519 /* struct rvu_af_pfx_vf_bar4_addr_s cn; */
520 };
521
522 static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a)
523 __attribute__ ((pure, always_inline));
RVU_AF_PFX_VF_BAR4_ADDR(u64 a)524 static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a)
525 {
526 return 0x1000 + 0x10 * a;
527 }
528
529 /**
530 * Register (RVU_PF_BAR0) rvu_af_pf_bar4_addr
531 *
532 * RVU Admin Function PF BAR4 Address Registers
533 */
534 union rvu_af_pf_bar4_addr {
535 u64 u;
536 struct rvu_af_pf_bar4_addr_s {
537 u64 reserved_0_15 : 16;
538 u64 addr : 48;
539 } s;
540 /* struct rvu_af_pf_bar4_addr_s cn; */
541 };
542
543 static inline u64 RVU_AF_PF_BAR4_ADDR(void)
544 __attribute__ ((pure, always_inline));
RVU_AF_PF_BAR4_ADDR(void)545 static inline u64 RVU_AF_PF_BAR4_ADDR(void)
546 {
547 return 0x40;
548 }
549
550 /**
551 * Register (RVU_PF_BAR0) rvu_af_pf_rst
552 *
553 * RVU Admin Function PF Reset Register
554 */
555 union rvu_af_pf_rst {
556 u64 u;
557 struct rvu_af_pf_rst_s {
558 u64 pf : 4;
559 u64 reserved_4_11 : 8;
560 u64 exec : 1;
561 u64 reserved_13_63 : 51;
562 } s;
563 /* struct rvu_af_pf_rst_s cn; */
564 };
565
566 static inline u64 RVU_AF_PF_RST(void)
567 __attribute__ ((pure, always_inline));
RVU_AF_PF_RST(void)568 static inline u64 RVU_AF_PF_RST(void)
569 {
570 return 0x2840;
571 }
572
573 /**
574 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int
575 *
576 * RVU Admin Function PF to AF Mailbox Interrupt Registers
577 */
578 union rvu_af_pfaf_mbox_int {
579 u64 u;
580 struct rvu_af_pfaf_mbox_int_s {
581 u64 mbox : 16;
582 u64 reserved_16_63 : 48;
583 } s;
584 /* struct rvu_af_pfaf_mbox_int_s cn; */
585 };
586
587 static inline u64 RVU_AF_PFAF_MBOX_INT(void)
588 __attribute__ ((pure, always_inline));
RVU_AF_PFAF_MBOX_INT(void)589 static inline u64 RVU_AF_PFAF_MBOX_INT(void)
590 {
591 return 0x2880;
592 }
593
594 /**
595 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1c
596 *
597 * RVU Admin Function PF to AF Mailbox Interrupt Enable Clear Registers
598 * This register clears interrupt enable bits.
599 */
600 union rvu_af_pfaf_mbox_int_ena_w1c {
601 u64 u;
602 struct rvu_af_pfaf_mbox_int_ena_w1c_s {
603 u64 mbox : 16;
604 u64 reserved_16_63 : 48;
605 } s;
606 /* struct rvu_af_pfaf_mbox_int_ena_w1c_s cn; */
607 };
608
609 static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void)
610 __attribute__ ((pure, always_inline));
RVU_AF_PFAF_MBOX_INT_ENA_W1C(void)611 static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void)
612 {
613 return 0x2898;
614 }
615
616 /**
617 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1s
618 *
619 * RVU Admin Function PF to AF Mailbox Interrupt Enable Set Registers
620 * This register sets interrupt enable bits.
621 */
622 union rvu_af_pfaf_mbox_int_ena_w1s {
623 u64 u;
624 struct rvu_af_pfaf_mbox_int_ena_w1s_s {
625 u64 mbox : 16;
626 u64 reserved_16_63 : 48;
627 } s;
628 /* struct rvu_af_pfaf_mbox_int_ena_w1s_s cn; */
629 };
630
631 static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void)
632 __attribute__ ((pure, always_inline));
RVU_AF_PFAF_MBOX_INT_ENA_W1S(void)633 static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void)
634 {
635 return 0x2890;
636 }
637
638 /**
639 * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_w1s
640 *
641 * RVU Admin Function PF to AF Mailbox Interrupt Set Registers This
642 * register sets interrupt bits.
643 */
644 union rvu_af_pfaf_mbox_int_w1s {
645 u64 u;
646 struct rvu_af_pfaf_mbox_int_w1s_s {
647 u64 mbox : 16;
648 u64 reserved_16_63 : 48;
649 } s;
650 /* struct rvu_af_pfaf_mbox_int_w1s_s cn; */
651 };
652
653 static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void)
654 __attribute__ ((pure, always_inline));
RVU_AF_PFAF_MBOX_INT_W1S(void)655 static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void)
656 {
657 return 0x2888;
658 }
659
660 /**
661 * Register (RVU_PF_BAR0) rvu_af_pfflr_int
662 *
663 * RVU Admin Function PF Function Level Reset Interrupt Registers
664 */
665 union rvu_af_pfflr_int {
666 u64 u;
667 struct rvu_af_pfflr_int_s {
668 u64 flr : 16;
669 u64 reserved_16_63 : 48;
670 } s;
671 /* struct rvu_af_pfflr_int_s cn; */
672 };
673
674 static inline u64 RVU_AF_PFFLR_INT(void)
675 __attribute__ ((pure, always_inline));
RVU_AF_PFFLR_INT(void)676 static inline u64 RVU_AF_PFFLR_INT(void)
677 {
678 return 0x28a0;
679 }
680
681 /**
682 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1c
683 *
684 * RVU Admin Function PF Function Level Reset Interrupt Enable Clear
685 * Registers This register clears interrupt enable bits.
686 */
687 union rvu_af_pfflr_int_ena_w1c {
688 u64 u;
689 struct rvu_af_pfflr_int_ena_w1c_s {
690 u64 flr : 16;
691 u64 reserved_16_63 : 48;
692 } s;
693 /* struct rvu_af_pfflr_int_ena_w1c_s cn; */
694 };
695
696 static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void)
697 __attribute__ ((pure, always_inline));
RVU_AF_PFFLR_INT_ENA_W1C(void)698 static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void)
699 {
700 return 0x28b8;
701 }
702
703 /**
704 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1s
705 *
706 * RVU Admin Function PF Function Level Reset Interrupt Enable Set
707 * Registers This register sets interrupt enable bits.
708 */
709 union rvu_af_pfflr_int_ena_w1s {
710 u64 u;
711 struct rvu_af_pfflr_int_ena_w1s_s {
712 u64 flr : 16;
713 u64 reserved_16_63 : 48;
714 } s;
715 /* struct rvu_af_pfflr_int_ena_w1s_s cn; */
716 };
717
718 static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void)
719 __attribute__ ((pure, always_inline));
RVU_AF_PFFLR_INT_ENA_W1S(void)720 static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void)
721 {
722 return 0x28b0;
723 }
724
725 /**
726 * Register (RVU_PF_BAR0) rvu_af_pfflr_int_w1s
727 *
728 * RVU Admin Function PF Function Level Reset Interrupt Set Registers
729 * This register sets interrupt bits.
730 */
731 union rvu_af_pfflr_int_w1s {
732 u64 u;
733 struct rvu_af_pfflr_int_w1s_s {
734 u64 flr : 16;
735 u64 reserved_16_63 : 48;
736 } s;
737 /* struct rvu_af_pfflr_int_w1s_s cn; */
738 };
739
740 static inline u64 RVU_AF_PFFLR_INT_W1S(void)
741 __attribute__ ((pure, always_inline));
RVU_AF_PFFLR_INT_W1S(void)742 static inline u64 RVU_AF_PFFLR_INT_W1S(void)
743 {
744 return 0x28a8;
745 }
746
747 /**
748 * Register (RVU_PF_BAR0) rvu_af_pfme_int
749 *
750 * RVU Admin Function PF Bus Master Enable Interrupt Registers
751 */
752 union rvu_af_pfme_int {
753 u64 u;
754 struct rvu_af_pfme_int_s {
755 u64 me : 16;
756 u64 reserved_16_63 : 48;
757 } s;
758 /* struct rvu_af_pfme_int_s cn; */
759 };
760
761 static inline u64 RVU_AF_PFME_INT(void)
762 __attribute__ ((pure, always_inline));
RVU_AF_PFME_INT(void)763 static inline u64 RVU_AF_PFME_INT(void)
764 {
765 return 0x28c0;
766 }
767
768 /**
769 * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1c
770 *
771 * RVU Admin Function PF Bus Master Enable Interrupt Enable Clear
772 * Registers This register clears interrupt enable bits.
773 */
774 union rvu_af_pfme_int_ena_w1c {
775 u64 u;
776 struct rvu_af_pfme_int_ena_w1c_s {
777 u64 me : 16;
778 u64 reserved_16_63 : 48;
779 } s;
780 /* struct rvu_af_pfme_int_ena_w1c_s cn; */
781 };
782
783 static inline u64 RVU_AF_PFME_INT_ENA_W1C(void)
784 __attribute__ ((pure, always_inline));
RVU_AF_PFME_INT_ENA_W1C(void)785 static inline u64 RVU_AF_PFME_INT_ENA_W1C(void)
786 {
787 return 0x28d8;
788 }
789
790 /**
791 * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1s
792 *
793 * RVU Admin Function PF Bus Master Enable Interrupt Enable Set Registers
794 * This register sets interrupt enable bits.
795 */
796 union rvu_af_pfme_int_ena_w1s {
797 u64 u;
798 struct rvu_af_pfme_int_ena_w1s_s {
799 u64 me : 16;
800 u64 reserved_16_63 : 48;
801 } s;
802 /* struct rvu_af_pfme_int_ena_w1s_s cn; */
803 };
804
805 static inline u64 RVU_AF_PFME_INT_ENA_W1S(void)
806 __attribute__ ((pure, always_inline));
RVU_AF_PFME_INT_ENA_W1S(void)807 static inline u64 RVU_AF_PFME_INT_ENA_W1S(void)
808 {
809 return 0x28d0;
810 }
811
812 /**
813 * Register (RVU_PF_BAR0) rvu_af_pfme_int_w1s
814 *
815 * RVU Admin Function PF Bus Master Enable Interrupt Set Registers This
816 * register sets interrupt bits.
817 */
818 union rvu_af_pfme_int_w1s {
819 u64 u;
820 struct rvu_af_pfme_int_w1s_s {
821 u64 me : 16;
822 u64 reserved_16_63 : 48;
823 } s;
824 /* struct rvu_af_pfme_int_w1s_s cn; */
825 };
826
827 static inline u64 RVU_AF_PFME_INT_W1S(void)
828 __attribute__ ((pure, always_inline));
RVU_AF_PFME_INT_W1S(void)829 static inline u64 RVU_AF_PFME_INT_W1S(void)
830 {
831 return 0x28c8;
832 }
833
834 /**
835 * Register (RVU_PF_BAR0) rvu_af_pfme_status
836 *
837 * RVU Admin Function PF Bus Master Enable Status Registers
838 */
839 union rvu_af_pfme_status {
840 u64 u;
841 struct rvu_af_pfme_status_s {
842 u64 me : 16;
843 u64 reserved_16_63 : 48;
844 } s;
845 /* struct rvu_af_pfme_status_s cn; */
846 };
847
848 static inline u64 RVU_AF_PFME_STATUS(void)
849 __attribute__ ((pure, always_inline));
RVU_AF_PFME_STATUS(void)850 static inline u64 RVU_AF_PFME_STATUS(void)
851 {
852 return 0x2800;
853 }
854
855 /**
856 * Register (RVU_PF_BAR0) rvu_af_pftrpend
857 *
858 * RVU Admin Function PF Transaction Pending Registers
859 */
860 union rvu_af_pftrpend {
861 u64 u;
862 struct rvu_af_pftrpend_s {
863 u64 trpend : 16;
864 u64 reserved_16_63 : 48;
865 } s;
866 /* struct rvu_af_pftrpend_s cn; */
867 };
868
869 static inline u64 RVU_AF_PFTRPEND(void)
870 __attribute__ ((pure, always_inline));
RVU_AF_PFTRPEND(void)871 static inline u64 RVU_AF_PFTRPEND(void)
872 {
873 return 0x2810;
874 }
875
876 /**
877 * Register (RVU_PF_BAR0) rvu_af_pftrpend_w1s
878 *
879 * RVU Admin Function PF Transaction Pending Set Registers This register
880 * reads or sets bits.
881 */
882 union rvu_af_pftrpend_w1s {
883 u64 u;
884 struct rvu_af_pftrpend_w1s_s {
885 u64 trpend : 16;
886 u64 reserved_16_63 : 48;
887 } s;
888 /* struct rvu_af_pftrpend_w1s_s cn; */
889 };
890
891 static inline u64 RVU_AF_PFTRPEND_W1S(void)
892 __attribute__ ((pure, always_inline));
RVU_AF_PFTRPEND_W1S(void)893 static inline u64 RVU_AF_PFTRPEND_W1S(void)
894 {
895 return 0x2820;
896 }
897
898 /**
899 * Register (RVU_PF_BAR0) rvu_af_ras
900 *
901 * RVU Admin Function RAS Interrupt Register This register is intended
902 * for delivery of RAS events to the SCP, so should be ignored by OS
903 * drivers.
904 */
905 union rvu_af_ras {
906 u64 u;
907 struct rvu_af_ras_s {
908 u64 msix_poison : 1;
909 u64 reserved_1_63 : 63;
910 } s;
911 /* struct rvu_af_ras_s cn; */
912 };
913
914 static inline u64 RVU_AF_RAS(void)
915 __attribute__ ((pure, always_inline));
RVU_AF_RAS(void)916 static inline u64 RVU_AF_RAS(void)
917 {
918 return 0x100;
919 }
920
921 /**
922 * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1c
923 *
924 * RVU Admin Function RAS Interrupt Enable Clear Register This register
925 * clears interrupt enable bits.
926 */
927 union rvu_af_ras_ena_w1c {
928 u64 u;
929 struct rvu_af_ras_ena_w1c_s {
930 u64 msix_poison : 1;
931 u64 reserved_1_63 : 63;
932 } s;
933 /* struct rvu_af_ras_ena_w1c_s cn; */
934 };
935
936 static inline u64 RVU_AF_RAS_ENA_W1C(void)
937 __attribute__ ((pure, always_inline));
RVU_AF_RAS_ENA_W1C(void)938 static inline u64 RVU_AF_RAS_ENA_W1C(void)
939 {
940 return 0x118;
941 }
942
943 /**
944 * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1s
945 *
946 * RVU Admin Function RAS Interrupt Enable Set Register This register
947 * sets interrupt enable bits.
948 */
949 union rvu_af_ras_ena_w1s {
950 u64 u;
951 struct rvu_af_ras_ena_w1s_s {
952 u64 msix_poison : 1;
953 u64 reserved_1_63 : 63;
954 } s;
955 /* struct rvu_af_ras_ena_w1s_s cn; */
956 };
957
958 static inline u64 RVU_AF_RAS_ENA_W1S(void)
959 __attribute__ ((pure, always_inline));
RVU_AF_RAS_ENA_W1S(void)960 static inline u64 RVU_AF_RAS_ENA_W1S(void)
961 {
962 return 0x110;
963 }
964
965 /**
966 * Register (RVU_PF_BAR0) rvu_af_ras_w1s
967 *
968 * RVU Admin Function RAS Interrupt Set Register This register sets
969 * interrupt bits.
970 */
971 union rvu_af_ras_w1s {
972 u64 u;
973 struct rvu_af_ras_w1s_s {
974 u64 msix_poison : 1;
975 u64 reserved_1_63 : 63;
976 } s;
977 /* struct rvu_af_ras_w1s_s cn; */
978 };
979
980 static inline u64 RVU_AF_RAS_W1S(void)
981 __attribute__ ((pure, always_inline));
RVU_AF_RAS_W1S(void)982 static inline u64 RVU_AF_RAS_W1S(void)
983 {
984 return 0x108;
985 }
986
987 /**
988 * Register (RVU_PF_BAR2) rvu_pf_block_addr#_disc
989 *
990 * RVU PF Block Address Discovery Registers These registers allow each PF
991 * driver to discover block resources that are provisioned to its PF. The
992 * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E.
993 */
994 union rvu_pf_block_addrx_disc {
995 u64 u;
996 struct rvu_pf_block_addrx_disc_s {
997 u64 num_lfs : 9;
998 u64 reserved_9_10 : 2;
999 u64 imp : 1;
1000 u64 rid : 8;
1001 u64 btype : 8;
1002 u64 reserved_28_63 : 36;
1003 } s;
1004 /* struct rvu_pf_block_addrx_disc_s cn; */
1005 };
1006
1007 static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a)
1008 __attribute__ ((pure, always_inline));
RVU_PF_BLOCK_ADDRX_DISC(u64 a)1009 static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a)
1010 {
1011 return 0x200 + 8 * a;
1012 }
1013
1014 /**
1015 * Register (RVU_PF_BAR2) rvu_pf_int
1016 *
1017 * RVU PF Interrupt Registers
1018 */
1019 union rvu_pf_int {
1020 u64 u;
1021 struct rvu_pf_int_s {
1022 u64 mbox : 1;
1023 u64 reserved_1_63 : 63;
1024 } s;
1025 /* struct rvu_pf_int_s cn; */
1026 };
1027
1028 static inline u64 RVU_PF_INT(void)
1029 __attribute__ ((pure, always_inline));
RVU_PF_INT(void)1030 static inline u64 RVU_PF_INT(void)
1031 {
1032 return 0xc20;
1033 }
1034
1035 /**
1036 * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1c
1037 *
1038 * RVU PF Interrupt Enable Clear Register This register clears interrupt
1039 * enable bits.
1040 */
1041 union rvu_pf_int_ena_w1c {
1042 u64 u;
1043 struct rvu_pf_int_ena_w1c_s {
1044 u64 mbox : 1;
1045 u64 reserved_1_63 : 63;
1046 } s;
1047 /* struct rvu_pf_int_ena_w1c_s cn; */
1048 };
1049
1050 static inline u64 RVU_PF_INT_ENA_W1C(void)
1051 __attribute__ ((pure, always_inline));
RVU_PF_INT_ENA_W1C(void)1052 static inline u64 RVU_PF_INT_ENA_W1C(void)
1053 {
1054 return 0xc38;
1055 }
1056
1057 /**
1058 * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1s
1059 *
1060 * RVU PF Interrupt Enable Set Register This register sets interrupt
1061 * enable bits.
1062 */
1063 union rvu_pf_int_ena_w1s {
1064 u64 u;
1065 struct rvu_pf_int_ena_w1s_s {
1066 u64 mbox : 1;
1067 u64 reserved_1_63 : 63;
1068 } s;
1069 /* struct rvu_pf_int_ena_w1s_s cn; */
1070 };
1071
1072 static inline u64 RVU_PF_INT_ENA_W1S(void)
1073 __attribute__ ((pure, always_inline));
RVU_PF_INT_ENA_W1S(void)1074 static inline u64 RVU_PF_INT_ENA_W1S(void)
1075 {
1076 return 0xc30;
1077 }
1078
1079 /**
1080 * Register (RVU_PF_BAR2) rvu_pf_int_w1s
1081 *
1082 * RVU PF Interrupt Set Register This register sets interrupt bits.
1083 */
1084 union rvu_pf_int_w1s {
1085 u64 u;
1086 struct rvu_pf_int_w1s_s {
1087 u64 mbox : 1;
1088 u64 reserved_1_63 : 63;
1089 } s;
1090 /* struct rvu_pf_int_w1s_s cn; */
1091 };
1092
1093 static inline u64 RVU_PF_INT_W1S(void)
1094 __attribute__ ((pure, always_inline));
RVU_PF_INT_W1S(void)1095 static inline u64 RVU_PF_INT_W1S(void)
1096 {
1097 return 0xc28;
1098 }
1099
1100 /**
1101 * Register (RVU_PF_BAR2) rvu_pf_msix_pba#
1102 *
1103 * RVU PF MSI-X Pending-Bit-Array Registers This register is the MSI-X PF
1104 * PBA table.
1105 */
1106 union rvu_pf_msix_pbax {
1107 u64 u;
1108 struct rvu_pf_msix_pbax_s {
1109 u64 pend : 64;
1110 } s;
1111 /* struct rvu_pf_msix_pbax_s cn; */
1112 };
1113
1114 static inline u64 RVU_PF_MSIX_PBAX(u64 a)
1115 __attribute__ ((pure, always_inline));
RVU_PF_MSIX_PBAX(u64 a)1116 static inline u64 RVU_PF_MSIX_PBAX(u64 a)
1117 {
1118 return 0xf0000 + 8 * a;
1119 }
1120
1121 /**
1122 * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_addr
1123 *
1124 * RVU PF MSI-X Vector-Table Address Registers These registers and
1125 * RVU_PF_MSIX_VEC()_CTL form the PF MSI-X vector table. The number of
1126 * MSI-X vectors for a given PF is specified by
1127 * RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1] (plus 1). Software must do a
1128 * read after any writes to the MSI-X vector table to ensure that the
1129 * writes have completed before interrupts are generated to the modified
1130 * vectors.
1131 */
1132 union rvu_pf_msix_vecx_addr {
1133 u64 u;
1134 struct rvu_pf_msix_vecx_addr_s {
1135 u64 secvec : 1;
1136 u64 reserved_1 : 1;
1137 u64 addr : 51;
1138 u64 reserved_53_63 : 11;
1139 } s;
1140 /* struct rvu_pf_msix_vecx_addr_s cn; */
1141 };
1142
1143 static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a)
1144 __attribute__ ((pure, always_inline));
RVU_PF_MSIX_VECX_ADDR(u64 a)1145 static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a)
1146 {
1147 return 0x80000 + 0x10 * a;
1148 }
1149
1150 /**
1151 * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_ctl
1152 *
1153 * RVU PF MSI-X Vector-Table Control and Data Registers These registers
1154 * and RVU_PF_MSIX_VEC()_ADDR form the PF MSI-X vector table.
1155 */
1156 union rvu_pf_msix_vecx_ctl {
1157 u64 u;
1158 struct rvu_pf_msix_vecx_ctl_s {
1159 u64 data : 32;
1160 u64 mask : 1;
1161 u64 reserved_33_63 : 31;
1162 } s;
1163 /* struct rvu_pf_msix_vecx_ctl_s cn; */
1164 };
1165
1166 static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a)
1167 __attribute__ ((pure, always_inline));
RVU_PF_MSIX_VECX_CTL(u64 a)1168 static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a)
1169 {
1170 return 0x80008 + 0x10 * a;
1171 }
1172
1173 /**
1174 * Register (RVU_PF_BAR2) rvu_pf_pfaf_mbox#
1175 *
1176 * RVU PF/AF Mailbox Registers
1177 */
1178 union rvu_pf_pfaf_mboxx {
1179 u64 u;
1180 struct rvu_pf_pfaf_mboxx_s {
1181 u64 data : 64;
1182 } s;
1183 /* struct rvu_pf_pfaf_mboxx_s cn; */
1184 };
1185
1186 static inline u64 RVU_PF_PFAF_MBOXX(u64 a)
1187 __attribute__ ((pure, always_inline));
RVU_PF_PFAF_MBOXX(u64 a)1188 static inline u64 RVU_PF_PFAF_MBOXX(u64 a)
1189 {
1190 return 0xc00 + 8 * a;
1191 }
1192
1193 /**
1194 * Register (RVU_PF_BAR2) rvu_pf_vf#_pfvf_mbox#
1195 *
1196 * RVU PF/VF Mailbox Registers
1197 */
1198 union rvu_pf_vfx_pfvf_mboxx {
1199 u64 u;
1200 struct rvu_pf_vfx_pfvf_mboxx_s {
1201 u64 data : 64;
1202 } s;
1203 /* struct rvu_pf_vfx_pfvf_mboxx_s cn; */
1204 };
1205
1206 static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b)
1207 __attribute__ ((pure, always_inline));
RVU_PF_VFX_PFVF_MBOXX(u64 a,u64 b)1208 static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b)
1209 {
1210 return 0 + 0x1000 * a + 8 * b;
1211 }
1212
1213 /**
1214 * Register (RVU_PF_BAR2) rvu_pf_vf_bar4_addr
1215 *
1216 * RVU PF VF BAR4 Address Registers
1217 */
1218 union rvu_pf_vf_bar4_addr {
1219 u64 u;
1220 struct rvu_pf_vf_bar4_addr_s {
1221 u64 reserved_0_15 : 16;
1222 u64 addr : 48;
1223 } s;
1224 /* struct rvu_pf_vf_bar4_addr_s cn; */
1225 };
1226
1227 static inline u64 RVU_PF_VF_BAR4_ADDR(void)
1228 __attribute__ ((pure, always_inline));
RVU_PF_VF_BAR4_ADDR(void)1229 static inline u64 RVU_PF_VF_BAR4_ADDR(void)
1230 {
1231 return 0x10;
1232 }
1233
1234 /**
1235 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int#
1236 *
1237 * RVU PF VF Function Level Reset Interrupt Registers
1238 */
1239 union rvu_pf_vfflr_intx {
1240 u64 u;
1241 struct rvu_pf_vfflr_intx_s {
1242 u64 flr : 64;
1243 } s;
1244 /* struct rvu_pf_vfflr_intx_s cn; */
1245 };
1246
1247 static inline u64 RVU_PF_VFFLR_INTX(u64 a)
1248 __attribute__ ((pure, always_inline));
RVU_PF_VFFLR_INTX(u64 a)1249 static inline u64 RVU_PF_VFFLR_INTX(u64 a)
1250 {
1251 return 0x900 + 8 * a;
1252 }
1253
1254 /**
1255 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1c#
1256 *
1257 * RVU PF VF Function Level Reset Interrupt Enable Clear Registers This
1258 * register clears interrupt enable bits.
1259 */
1260 union rvu_pf_vfflr_int_ena_w1cx {
1261 u64 u;
1262 struct rvu_pf_vfflr_int_ena_w1cx_s {
1263 u64 flr : 64;
1264 } s;
1265 /* struct rvu_pf_vfflr_int_ena_w1cx_s cn; */
1266 };
1267
1268 static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a)
1269 __attribute__ ((pure, always_inline));
RVU_PF_VFFLR_INT_ENA_W1CX(u64 a)1270 static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a)
1271 {
1272 return 0x960 + 8 * a;
1273 }
1274
1275 /**
1276 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1s#
1277 *
1278 * RVU PF VF Function Level Reset Interrupt Enable Set Registers This
1279 * register sets interrupt enable bits.
1280 */
1281 union rvu_pf_vfflr_int_ena_w1sx {
1282 u64 u;
1283 struct rvu_pf_vfflr_int_ena_w1sx_s {
1284 u64 flr : 64;
1285 } s;
1286 /* struct rvu_pf_vfflr_int_ena_w1sx_s cn; */
1287 };
1288
1289 static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a)
1290 __attribute__ ((pure, always_inline));
RVU_PF_VFFLR_INT_ENA_W1SX(u64 a)1291 static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a)
1292 {
1293 return 0x940 + 8 * a;
1294 }
1295
1296 /**
1297 * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_w1s#
1298 *
1299 * RVU PF VF Function Level Reset Interrupt Set Registers This register
1300 * sets interrupt bits.
1301 */
1302 union rvu_pf_vfflr_int_w1sx {
1303 u64 u;
1304 struct rvu_pf_vfflr_int_w1sx_s {
1305 u64 flr : 64;
1306 } s;
1307 /* struct rvu_pf_vfflr_int_w1sx_s cn; */
1308 };
1309
1310 static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a)
1311 __attribute__ ((pure, always_inline));
RVU_PF_VFFLR_INT_W1SX(u64 a)1312 static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a)
1313 {
1314 return 0x920 + 8 * a;
1315 }
1316
1317 /**
1318 * Register (RVU_PF_BAR2) rvu_pf_vfme_int#
1319 *
1320 * RVU PF VF Bus Master Enable Interrupt Registers
1321 */
1322 union rvu_pf_vfme_intx {
1323 u64 u;
1324 struct rvu_pf_vfme_intx_s {
1325 u64 me : 64;
1326 } s;
1327 /* struct rvu_pf_vfme_intx_s cn; */
1328 };
1329
1330 static inline u64 RVU_PF_VFME_INTX(u64 a)
1331 __attribute__ ((pure, always_inline));
RVU_PF_VFME_INTX(u64 a)1332 static inline u64 RVU_PF_VFME_INTX(u64 a)
1333 {
1334 return 0x980 + 8 * a;
1335 }
1336
1337 /**
1338 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1c#
1339 *
1340 * RVU PF VF Bus Master Enable Interrupt Enable Clear Registers This
1341 * register clears interrupt enable bits.
1342 */
1343 union rvu_pf_vfme_int_ena_w1cx {
1344 u64 u;
1345 struct rvu_pf_vfme_int_ena_w1cx_s {
1346 u64 me : 64;
1347 } s;
1348 /* struct rvu_pf_vfme_int_ena_w1cx_s cn; */
1349 };
1350
1351 static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a)
1352 __attribute__ ((pure, always_inline));
RVU_PF_VFME_INT_ENA_W1CX(u64 a)1353 static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a)
1354 {
1355 return 0x9e0 + 8 * a;
1356 }
1357
1358 /**
1359 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1s#
1360 *
1361 * RVU PF VF Bus Master Enable Interrupt Enable Set Registers This
1362 * register sets interrupt enable bits.
1363 */
1364 union rvu_pf_vfme_int_ena_w1sx {
1365 u64 u;
1366 struct rvu_pf_vfme_int_ena_w1sx_s {
1367 u64 me : 64;
1368 } s;
1369 /* struct rvu_pf_vfme_int_ena_w1sx_s cn; */
1370 };
1371
1372 static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a)
1373 __attribute__ ((pure, always_inline));
RVU_PF_VFME_INT_ENA_W1SX(u64 a)1374 static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a)
1375 {
1376 return 0x9c0 + 8 * a;
1377 }
1378
1379 /**
1380 * Register (RVU_PF_BAR2) rvu_pf_vfme_int_w1s#
1381 *
1382 * RVU PF VF Bus Master Enable Interrupt Set Registers This register sets
1383 * interrupt bits.
1384 */
1385 union rvu_pf_vfme_int_w1sx {
1386 u64 u;
1387 struct rvu_pf_vfme_int_w1sx_s {
1388 u64 me : 64;
1389 } s;
1390 /* struct rvu_pf_vfme_int_w1sx_s cn; */
1391 };
1392
1393 static inline u64 RVU_PF_VFME_INT_W1SX(u64 a)
1394 __attribute__ ((pure, always_inline));
RVU_PF_VFME_INT_W1SX(u64 a)1395 static inline u64 RVU_PF_VFME_INT_W1SX(u64 a)
1396 {
1397 return 0x9a0 + 8 * a;
1398 }
1399
1400 /**
1401 * Register (RVU_PF_BAR2) rvu_pf_vfme_status#
1402 *
1403 * RVU PF VF Bus Master Enable Status Registers
1404 */
1405 union rvu_pf_vfme_statusx {
1406 u64 u;
1407 struct rvu_pf_vfme_statusx_s {
1408 u64 me : 64;
1409 } s;
1410 /* struct rvu_pf_vfme_statusx_s cn; */
1411 };
1412
1413 static inline u64 RVU_PF_VFME_STATUSX(u64 a)
1414 __attribute__ ((pure, always_inline));
RVU_PF_VFME_STATUSX(u64 a)1415 static inline u64 RVU_PF_VFME_STATUSX(u64 a)
1416 {
1417 return 0x800 + 8 * a;
1418 }
1419
1420 /**
1421 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int#
1422 *
1423 * RVU VF to PF Mailbox Interrupt Registers
1424 */
1425 union rvu_pf_vfpf_mbox_intx {
1426 u64 u;
1427 struct rvu_pf_vfpf_mbox_intx_s {
1428 u64 mbox : 64;
1429 } s;
1430 /* struct rvu_pf_vfpf_mbox_intx_s cn; */
1431 };
1432
1433 static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a)
1434 __attribute__ ((pure, always_inline));
RVU_PF_VFPF_MBOX_INTX(u64 a)1435 static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a)
1436 {
1437 return 0x880 + 8 * a;
1438 }
1439
1440 /**
1441 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1c#
1442 *
1443 * RVU VF to PF Mailbox Interrupt Enable Clear Registers This register
1444 * clears interrupt enable bits.
1445 */
1446 union rvu_pf_vfpf_mbox_int_ena_w1cx {
1447 u64 u;
1448 struct rvu_pf_vfpf_mbox_int_ena_w1cx_s {
1449 u64 mbox : 64;
1450 } s;
1451 /* struct rvu_pf_vfpf_mbox_int_ena_w1cx_s cn; */
1452 };
1453
1454 static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a)
1455 __attribute__ ((pure, always_inline));
RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a)1456 static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a)
1457 {
1458 return 0x8e0 + 8 * a;
1459 }
1460
1461 /**
1462 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1s#
1463 *
1464 * RVU VF to PF Mailbox Interrupt Enable Set Registers This register sets
1465 * interrupt enable bits.
1466 */
1467 union rvu_pf_vfpf_mbox_int_ena_w1sx {
1468 u64 u;
1469 struct rvu_pf_vfpf_mbox_int_ena_w1sx_s {
1470 u64 mbox : 64;
1471 } s;
1472 /* struct rvu_pf_vfpf_mbox_int_ena_w1sx_s cn; */
1473 };
1474
1475 static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a)
1476 __attribute__ ((pure, always_inline));
RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a)1477 static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a)
1478 {
1479 return 0x8c0 + 8 * a;
1480 }
1481
1482 /**
1483 * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_w1s#
1484 *
1485 * RVU VF to PF Mailbox Interrupt Set Registers This register sets
1486 * interrupt bits.
1487 */
1488 union rvu_pf_vfpf_mbox_int_w1sx {
1489 u64 u;
1490 struct rvu_pf_vfpf_mbox_int_w1sx_s {
1491 u64 mbox : 64;
1492 } s;
1493 /* struct rvu_pf_vfpf_mbox_int_w1sx_s cn; */
1494 };
1495
1496 static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a)
1497 __attribute__ ((pure, always_inline));
RVU_PF_VFPF_MBOX_INT_W1SX(u64 a)1498 static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a)
1499 {
1500 return 0x8a0 + 8 * a;
1501 }
1502
1503 /**
1504 * Register (RVU_PF_BAR2) rvu_pf_vftrpend#
1505 *
1506 * RVU PF VF Transaction Pending Registers
1507 */
1508 union rvu_pf_vftrpendx {
1509 u64 u;
1510 struct rvu_pf_vftrpendx_s {
1511 u64 trpend : 64;
1512 } s;
1513 /* struct rvu_pf_vftrpendx_s cn; */
1514 };
1515
1516 static inline u64 RVU_PF_VFTRPENDX(u64 a)
1517 __attribute__ ((pure, always_inline));
RVU_PF_VFTRPENDX(u64 a)1518 static inline u64 RVU_PF_VFTRPENDX(u64 a)
1519 {
1520 return 0x820 + 8 * a;
1521 }
1522
1523 /**
1524 * Register (RVU_PF_BAR2) rvu_pf_vftrpend_w1s#
1525 *
1526 * RVU PF VF Transaction Pending Set Registers This register reads or
1527 * sets bits.
1528 */
1529 union rvu_pf_vftrpend_w1sx {
1530 u64 u;
1531 struct rvu_pf_vftrpend_w1sx_s {
1532 u64 trpend : 64;
1533 } s;
1534 /* struct rvu_pf_vftrpend_w1sx_s cn; */
1535 };
1536
1537 static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a)
1538 __attribute__ ((pure, always_inline));
RVU_PF_VFTRPEND_W1SX(u64 a)1539 static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a)
1540 {
1541 return 0x840 + 8 * a;
1542 }
1543
1544 /**
1545 * Register (RVU_PF_BAR0) rvu_priv_active_pc
1546 *
1547 * RVU Active Program Counter Register
1548 */
1549 union rvu_priv_active_pc {
1550 u64 u;
1551 struct rvu_priv_active_pc_s {
1552 u64 active_pc : 64;
1553 } s;
1554 /* struct rvu_priv_active_pc_s cn; */
1555 };
1556
1557 static inline u64 RVU_PRIV_ACTIVE_PC(void)
1558 __attribute__ ((pure, always_inline));
RVU_PRIV_ACTIVE_PC(void)1559 static inline u64 RVU_PRIV_ACTIVE_PC(void)
1560 {
1561 return 0x8000030;
1562 }
1563
1564 /**
1565 * Register (RVU_PF_BAR0) rvu_priv_block_type#_rev
1566 *
1567 * RVU Privileged Block Type Revision Registers These registers are used
1568 * by configuration software to specify the revision ID of each block
1569 * type enumerated by RVU_BLOCK_TYPE_E, to assist VF/PF software
1570 * discovery.
1571 */
1572 union rvu_priv_block_typex_rev {
1573 u64 u;
1574 struct rvu_priv_block_typex_rev_s {
1575 u64 rid : 8;
1576 u64 reserved_8_63 : 56;
1577 } s;
1578 /* struct rvu_priv_block_typex_rev_s cn; */
1579 };
1580
1581 static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a)
1582 __attribute__ ((pure, always_inline));
RVU_PRIV_BLOCK_TYPEX_REV(u64 a)1583 static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a)
1584 {
1585 return 0x8000400 + 8 * a;
1586 }
1587
1588 /**
1589 * Register (RVU_PF_BAR0) rvu_priv_clk_cfg
1590 *
1591 * RVU Privileged General Configuration Register
1592 */
1593 union rvu_priv_clk_cfg {
1594 u64 u;
1595 struct rvu_priv_clk_cfg_s {
1596 u64 blk_clken : 1;
1597 u64 ncbi_clken : 1;
1598 u64 reserved_2_63 : 62;
1599 } s;
1600 /* struct rvu_priv_clk_cfg_s cn; */
1601 };
1602
1603 static inline u64 RVU_PRIV_CLK_CFG(void)
1604 __attribute__ ((pure, always_inline));
RVU_PRIV_CLK_CFG(void)1605 static inline u64 RVU_PRIV_CLK_CFG(void)
1606 {
1607 return 0x8000020;
1608 }
1609
1610 /**
1611 * Register (RVU_PF_BAR0) rvu_priv_const
1612 *
1613 * RVU Privileged Constants Register This register contains constants for
1614 * software discovery.
1615 */
1616 union rvu_priv_const {
1617 u64 u;
1618 struct rvu_priv_const_s {
1619 u64 max_msix : 20;
1620 u64 hwvfs : 12;
1621 u64 pfs : 8;
1622 u64 max_vfs_per_pf : 8;
1623 u64 reserved_48_63 : 16;
1624 } s;
1625 /* struct rvu_priv_const_s cn; */
1626 };
1627
1628 static inline u64 RVU_PRIV_CONST(void)
1629 __attribute__ ((pure, always_inline));
RVU_PRIV_CONST(void)1630 static inline u64 RVU_PRIV_CONST(void)
1631 {
1632 return 0x8000000;
1633 }
1634
1635 /**
1636 * Register (RVU_PF_BAR0) rvu_priv_gen_cfg
1637 *
1638 * RVU Privileged General Configuration Register
1639 */
1640 union rvu_priv_gen_cfg {
1641 u64 u;
1642 struct rvu_priv_gen_cfg_s {
1643 u64 lock : 1;
1644 u64 reserved_1_63 : 63;
1645 } s;
1646 /* struct rvu_priv_gen_cfg_s cn; */
1647 };
1648
1649 static inline u64 RVU_PRIV_GEN_CFG(void)
1650 __attribute__ ((pure, always_inline));
RVU_PRIV_GEN_CFG(void)1651 static inline u64 RVU_PRIV_GEN_CFG(void)
1652 {
1653 return 0x8000010;
1654 }
1655
1656 /**
1657 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_cpt#_cfg
1658 *
1659 * RVU Privileged Hardware VF CPT Configuration Registers Similar to
1660 * RVU_PRIV_HWVF()_NIX()_CFG, but for CPT({a}) block.
1661 */
1662 union rvu_priv_hwvfx_cptx_cfg {
1663 u64 u;
1664 struct rvu_priv_hwvfx_cptx_cfg_s {
1665 u64 num_lfs : 9;
1666 u64 reserved_9_63 : 55;
1667 } s;
1668 /* struct rvu_priv_hwvfx_cptx_cfg_s cn; */
1669 };
1670
1671 static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b)
1672 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_CPTX_CFG(u64 a,u64 b)1673 static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b)
1674 {
1675 return 0x8001350 + 0x10000 * a + 8 * b;
1676 }
1677
1678 /**
1679 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_int_cfg
1680 *
1681 * RVU Privileged Hardware VF Interrupt Configuration Registers
1682 */
1683 union rvu_priv_hwvfx_int_cfg {
1684 u64 u;
1685 struct rvu_priv_hwvfx_int_cfg_s {
1686 u64 msix_offset : 11;
1687 u64 reserved_11 : 1;
1688 u64 msix_size : 8;
1689 u64 reserved_20_63 : 44;
1690 } s;
1691 /* struct rvu_priv_hwvfx_int_cfg_s cn; */
1692 };
1693
1694 static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a)
1695 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_INT_CFG(u64 a)1696 static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a)
1697 {
1698 return 0x8001280 + 0x10000 * a;
1699 }
1700
1701 /**
1702 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_nix#_cfg
1703 *
1704 * RVU Privileged Hardware VF NIX Configuration Registers These registers
1705 * are used to assist VF software discovery. For each HWVF, if the HWVF
1706 * is mapped to a VF by RVU_PRIV_PF()_CFG[FIRST_HWVF,NVF], software
1707 * writes NIX block's resource configuration for the VF in this register.
1708 * The VF driver can read RVU_VF_BLOCK_ADDR()_DISC to discover the
1709 * configuration.
1710 */
1711 union rvu_priv_hwvfx_nixx_cfg {
1712 u64 u;
1713 struct rvu_priv_hwvfx_nixx_cfg_s {
1714 u64 has_lf : 1;
1715 u64 reserved_1_63 : 63;
1716 } s;
1717 /* struct rvu_priv_hwvfx_nixx_cfg_s cn; */
1718 };
1719
1720 static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b)
1721 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_NIXX_CFG(u64 a,u64 b)1722 static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b)
1723 {
1724 return 0x8001300 + 0x10000 * a + 8 * b;
1725 }
1726
1727 /**
1728 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_npa_cfg
1729 *
1730 * RVU Privileged Hardware VF NPA Configuration Registers Similar to
1731 * RVU_PRIV_HWVF()_NIX()_CFG, but for NPA block.
1732 */
1733 union rvu_priv_hwvfx_npa_cfg {
1734 u64 u;
1735 struct rvu_priv_hwvfx_npa_cfg_s {
1736 u64 has_lf : 1;
1737 u64 reserved_1_63 : 63;
1738 } s;
1739 /* struct rvu_priv_hwvfx_npa_cfg_s cn; */
1740 };
1741
1742 static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a)
1743 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_NPA_CFG(u64 a)1744 static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a)
1745 {
1746 return 0x8001310 + 0x10000 * a;
1747 }
1748
1749 /**
1750 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_sso_cfg
1751 *
1752 * RVU Privileged Hardware VF SSO Configuration Registers Similar to
1753 * RVU_PRIV_HWVF()_NIX()_CFG, but for SSO block.
1754 */
1755 union rvu_priv_hwvfx_sso_cfg {
1756 u64 u;
1757 struct rvu_priv_hwvfx_sso_cfg_s {
1758 u64 num_lfs : 9;
1759 u64 reserved_9_63 : 55;
1760 } s;
1761 /* struct rvu_priv_hwvfx_sso_cfg_s cn; */
1762 };
1763
1764 static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a)
1765 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_SSO_CFG(u64 a)1766 static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a)
1767 {
1768 return 0x8001320 + 0x10000 * a;
1769 }
1770
1771 /**
1772 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_ssow_cfg
1773 *
1774 * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
1775 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for SSOW block.
1776 */
1777 union rvu_priv_hwvfx_ssow_cfg {
1778 u64 u;
1779 struct rvu_priv_hwvfx_ssow_cfg_s {
1780 u64 num_lfs : 9;
1781 u64 reserved_9_63 : 55;
1782 } s;
1783 /* struct rvu_priv_hwvfx_ssow_cfg_s cn; */
1784 };
1785
1786 static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a)
1787 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_SSOW_CFG(u64 a)1788 static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a)
1789 {
1790 return 0x8001330 + 0x10000 * a;
1791 }
1792
1793 /**
1794 * Register (RVU_PF_BAR0) rvu_priv_hwvf#_tim_cfg
1795 *
1796 * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
1797 * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for TIM block.
1798 */
1799 union rvu_priv_hwvfx_tim_cfg {
1800 u64 u;
1801 struct rvu_priv_hwvfx_tim_cfg_s {
1802 u64 num_lfs : 9;
1803 u64 reserved_9_63 : 55;
1804 } s;
1805 /* struct rvu_priv_hwvfx_tim_cfg_s cn; */
1806 };
1807
1808 static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a)
1809 __attribute__ ((pure, always_inline));
RVU_PRIV_HWVFX_TIM_CFG(u64 a)1810 static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a)
1811 {
1812 return 0x8001340 + 0x10000 * a;
1813 }
1814
1815 /**
1816 * Register (RVU_PF_BAR0) rvu_priv_pf#_cfg
1817 *
1818 * RVU Privileged PF Configuration Registers
1819 */
1820 union rvu_priv_pfx_cfg {
1821 u64 u;
1822 struct rvu_priv_pfx_cfg_s {
1823 u64 first_hwvf : 12;
1824 u64 nvf : 8;
1825 u64 ena : 1;
1826 u64 af_ena : 1;
1827 u64 me_flr_ena : 1;
1828 u64 pf_vf_io_bar4 : 1;
1829 u64 reserved_24_63 : 40;
1830 } s;
1831 struct rvu_priv_pfx_cfg_cn96xxp1 {
1832 u64 first_hwvf : 12;
1833 u64 nvf : 8;
1834 u64 ena : 1;
1835 u64 af_ena : 1;
1836 u64 me_flr_ena : 1;
1837 u64 reserved_23_63 : 41;
1838 } cn96xxp1;
1839 /* struct rvu_priv_pfx_cfg_s cn96xxp3; */
1840 /* struct rvu_priv_pfx_cfg_cn96xxp1 cnf95xx; */
1841 };
1842
1843 static inline u64 RVU_PRIV_PFX_CFG(u64 a)
1844 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_CFG(u64 a)1845 static inline u64 RVU_PRIV_PFX_CFG(u64 a)
1846 {
1847 return 0x8000100 + 0x10000 * a;
1848 }
1849
1850 /**
1851 * Register (RVU_PF_BAR0) rvu_priv_pf#_cpt#_cfg
1852 *
1853 * RVU Privileged PF CPT Configuration Registers Similar to
1854 * RVU_PRIV_PF()_NIX()_CFG, but for CPT({a}) block.
1855 */
1856 union rvu_priv_pfx_cptx_cfg {
1857 u64 u;
1858 struct rvu_priv_pfx_cptx_cfg_s {
1859 u64 num_lfs : 9;
1860 u64 reserved_9_63 : 55;
1861 } s;
1862 /* struct rvu_priv_pfx_cptx_cfg_s cn; */
1863 };
1864
1865 static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b)
1866 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_CPTX_CFG(u64 a,u64 b)1867 static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b)
1868 {
1869 return 0x8000350 + 0x10000 * a + 8 * b;
1870 }
1871
1872 /**
1873 * Register (RVU_PF_BAR0) rvu_priv_pf#_id_cfg
1874 *
1875 * RVU Privileged PF ID Configuration Registers
1876 */
1877 union rvu_priv_pfx_id_cfg {
1878 u64 u;
1879 struct rvu_priv_pfx_id_cfg_s {
1880 u64 pf_devid : 8;
1881 u64 vf_devid : 8;
1882 u64 class_code : 24;
1883 u64 reserved_40_63 : 24;
1884 } s;
1885 /* struct rvu_priv_pfx_id_cfg_s cn; */
1886 };
1887
1888 static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a)
1889 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_ID_CFG(u64 a)1890 static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a)
1891 {
1892 return 0x8000120 + 0x10000 * a;
1893 }
1894
1895 /**
1896 * Register (RVU_PF_BAR0) rvu_priv_pf#_int_cfg
1897 *
1898 * RVU Privileged PF Interrupt Configuration Registers
1899 */
1900 union rvu_priv_pfx_int_cfg {
1901 u64 u;
1902 struct rvu_priv_pfx_int_cfg_s {
1903 u64 msix_offset : 11;
1904 u64 reserved_11 : 1;
1905 u64 msix_size : 8;
1906 u64 reserved_20_63 : 44;
1907 } s;
1908 /* struct rvu_priv_pfx_int_cfg_s cn; */
1909 };
1910
1911 static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a)
1912 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_INT_CFG(u64 a)1913 static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a)
1914 {
1915 return 0x8000200 + 0x10000 * a;
1916 }
1917
1918 /**
1919 * Register (RVU_PF_BAR0) rvu_priv_pf#_msix_cfg
1920 *
1921 * RVU Privileged PF MSI-X Configuration Registers These registers
1922 * specify MSI-X table sizes and locations for RVU PFs and associated
1923 * VFs. Hardware maintains all RVU MSI-X tables in a contiguous memory
1924 * region in LLC/DRAM called the MSI-X table region. The table region's
1925 * base AF IOVA is specified by RVU_AF_MSIXTR_BASE, and its size as a
1926 * multiple of 16-byte RVU_MSIX_VEC_S structures must be less than or
1927 * equal to RVU_PRIV_CONST[MAX_MSIX]. A PF's MSI-X table consists of the
1928 * following range of RVU_MSIX_VEC_S structures in the table region: *
1929 * First index: [PF_MSIXT_OFFSET]. * Last index: [PF_MSIXT_OFFSET] +
1930 * [PF_MSIXT_SIZEM1]. If a PF has enabled VFs (associated
1931 * RVU_PRIV_PF()_CFG[NVF] is nonzero), then each VF's MSI-X table
1932 * consumes the following range of RVU_MSIX_VEC_S structures: * First
1933 * index: [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1). * Last index:
1934 * [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1) + [VF_MSIXT_SIZEM1].
1935 * N=0 for the first VF, N=1 for the second VF, etc. Different PFs and
1936 * VFs must have non-overlapping vector ranges, and the last index of any
1937 * range must be less than RVU_PRIV_CONST[MAX_MSIX].
1938 */
1939 union rvu_priv_pfx_msix_cfg {
1940 u64 u;
1941 struct rvu_priv_pfx_msix_cfg_s {
1942 u64 vf_msixt_sizem1 : 12;
1943 u64 vf_msixt_offset : 20;
1944 u64 pf_msixt_sizem1 : 12;
1945 u64 pf_msixt_offset : 20;
1946 } s;
1947 /* struct rvu_priv_pfx_msix_cfg_s cn; */
1948 };
1949
1950 static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a)
1951 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_MSIX_CFG(u64 a)1952 static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a)
1953 {
1954 return 0x8000110 + 0x10000 * a;
1955 }
1956
1957 /**
1958 * Register (RVU_PF_BAR0) rvu_priv_pf#_nix#_cfg
1959 *
1960 * RVU Privileged PF NIX Configuration Registers These registers are used
1961 * to assist PF software discovery. For each enabled RVU PF, software
1962 * writes the block's resource configuration for the PF in this register.
1963 * The PF driver can read RVU_PF_BLOCK_ADDR()_DISC to discover the
1964 * configuration.
1965 */
1966 union rvu_priv_pfx_nixx_cfg {
1967 u64 u;
1968 struct rvu_priv_pfx_nixx_cfg_s {
1969 u64 has_lf : 1;
1970 u64 reserved_1_63 : 63;
1971 } s;
1972 /* struct rvu_priv_pfx_nixx_cfg_s cn; */
1973 };
1974
1975 static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b)
1976 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_NIXX_CFG(u64 a,u64 b)1977 static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b)
1978 {
1979 return 0x8000300 + 0x10000 * a + 8 * b;
1980 }
1981
1982 /**
1983 * Register (RVU_PF_BAR0) rvu_priv_pf#_npa_cfg
1984 *
1985 * RVU Privileged PF NPA Configuration Registers Similar to
1986 * RVU_PRIV_PF()_NIX()_CFG, but for NPA block.
1987 */
1988 union rvu_priv_pfx_npa_cfg {
1989 u64 u;
1990 struct rvu_priv_pfx_npa_cfg_s {
1991 u64 has_lf : 1;
1992 u64 reserved_1_63 : 63;
1993 } s;
1994 /* struct rvu_priv_pfx_npa_cfg_s cn; */
1995 };
1996
1997 static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a)
1998 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_NPA_CFG(u64 a)1999 static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a)
2000 {
2001 return 0x8000310 + 0x10000 * a;
2002 }
2003
2004 /**
2005 * Register (RVU_PF_BAR0) rvu_priv_pf#_sso_cfg
2006 *
2007 * RVU Privileged PF SSO Configuration Registers Similar to
2008 * RVU_PRIV_PF()_NIX()_CFG, but for SSO block.
2009 */
2010 union rvu_priv_pfx_sso_cfg {
2011 u64 u;
2012 struct rvu_priv_pfx_sso_cfg_s {
2013 u64 num_lfs : 9;
2014 u64 reserved_9_63 : 55;
2015 } s;
2016 /* struct rvu_priv_pfx_sso_cfg_s cn; */
2017 };
2018
2019 static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a)
2020 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_SSO_CFG(u64 a)2021 static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a)
2022 {
2023 return 0x8000320 + 0x10000 * a;
2024 }
2025
2026 /**
2027 * Register (RVU_PF_BAR0) rvu_priv_pf#_ssow_cfg
2028 *
2029 * RVU Privileged PF SSO Work Slot Configuration Registers Similar to
2030 * RVU_PRIV_PF()_NIX()_CFG, but for SSOW block.
2031 */
2032 union rvu_priv_pfx_ssow_cfg {
2033 u64 u;
2034 struct rvu_priv_pfx_ssow_cfg_s {
2035 u64 num_lfs : 9;
2036 u64 reserved_9_63 : 55;
2037 } s;
2038 /* struct rvu_priv_pfx_ssow_cfg_s cn; */
2039 };
2040
2041 static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a)
2042 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_SSOW_CFG(u64 a)2043 static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a)
2044 {
2045 return 0x8000330 + 0x10000 * a;
2046 }
2047
2048 /**
2049 * Register (RVU_PF_BAR0) rvu_priv_pf#_tim_cfg
2050 *
2051 * RVU Privileged PF SSO Work Slot Configuration Registers Similar to
2052 * RVU_PRIV_PF()_NIX()_CFG, but for TIM block.
2053 */
2054 union rvu_priv_pfx_tim_cfg {
2055 u64 u;
2056 struct rvu_priv_pfx_tim_cfg_s {
2057 u64 num_lfs : 9;
2058 u64 reserved_9_63 : 55;
2059 } s;
2060 /* struct rvu_priv_pfx_tim_cfg_s cn; */
2061 };
2062
2063 static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a)
2064 __attribute__ ((pure, always_inline));
RVU_PRIV_PFX_TIM_CFG(u64 a)2065 static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a)
2066 {
2067 return 0x8000340 + 0x10000 * a;
2068 }
2069
2070 /**
2071 * Register (RVU_VF_BAR2) rvu_vf_block_addr#_disc
2072 *
2073 * RVU VF Block Address Discovery Registers These registers allow each VF
2074 * driver to discover block resources that are provisioned to its VF. The
2075 * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E.
2076 */
2077 union rvu_vf_block_addrx_disc {
2078 u64 u;
2079 struct rvu_vf_block_addrx_disc_s {
2080 u64 num_lfs : 9;
2081 u64 reserved_9_10 : 2;
2082 u64 imp : 1;
2083 u64 rid : 8;
2084 u64 btype : 8;
2085 u64 reserved_28_63 : 36;
2086 } s;
2087 /* struct rvu_vf_block_addrx_disc_s cn; */
2088 };
2089
2090 static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a)
2091 __attribute__ ((pure, always_inline));
RVU_VF_BLOCK_ADDRX_DISC(u64 a)2092 static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a)
2093 {
2094 return 0x200 + 8 * a;
2095 }
2096
2097 /**
2098 * Register (RVU_VF_BAR2) rvu_vf_int
2099 *
2100 * RVU VF Interrupt Registers
2101 */
2102 union rvu_vf_int {
2103 u64 u;
2104 struct rvu_vf_int_s {
2105 u64 mbox : 1;
2106 u64 reserved_1_63 : 63;
2107 } s;
2108 /* struct rvu_vf_int_s cn; */
2109 };
2110
2111 static inline u64 RVU_VF_INT(void)
2112 __attribute__ ((pure, always_inline));
RVU_VF_INT(void)2113 static inline u64 RVU_VF_INT(void)
2114 {
2115 return 0x20;
2116 }
2117
2118 /**
2119 * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1c
2120 *
2121 * RVU VF Interrupt Enable Clear Register This register clears interrupt
2122 * enable bits.
2123 */
2124 union rvu_vf_int_ena_w1c {
2125 u64 u;
2126 struct rvu_vf_int_ena_w1c_s {
2127 u64 mbox : 1;
2128 u64 reserved_1_63 : 63;
2129 } s;
2130 /* struct rvu_vf_int_ena_w1c_s cn; */
2131 };
2132
2133 static inline u64 RVU_VF_INT_ENA_W1C(void)
2134 __attribute__ ((pure, always_inline));
RVU_VF_INT_ENA_W1C(void)2135 static inline u64 RVU_VF_INT_ENA_W1C(void)
2136 {
2137 return 0x38;
2138 }
2139
2140 /**
2141 * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1s
2142 *
2143 * RVU VF Interrupt Enable Set Register This register sets interrupt
2144 * enable bits.
2145 */
2146 union rvu_vf_int_ena_w1s {
2147 u64 u;
2148 struct rvu_vf_int_ena_w1s_s {
2149 u64 mbox : 1;
2150 u64 reserved_1_63 : 63;
2151 } s;
2152 /* struct rvu_vf_int_ena_w1s_s cn; */
2153 };
2154
2155 static inline u64 RVU_VF_INT_ENA_W1S(void)
2156 __attribute__ ((pure, always_inline));
RVU_VF_INT_ENA_W1S(void)2157 static inline u64 RVU_VF_INT_ENA_W1S(void)
2158 {
2159 return 0x30;
2160 }
2161
2162 /**
2163 * Register (RVU_VF_BAR2) rvu_vf_int_w1s
2164 *
2165 * RVU VF Interrupt Set Register This register sets interrupt bits.
2166 */
2167 union rvu_vf_int_w1s {
2168 u64 u;
2169 struct rvu_vf_int_w1s_s {
2170 u64 mbox : 1;
2171 u64 reserved_1_63 : 63;
2172 } s;
2173 /* struct rvu_vf_int_w1s_s cn; */
2174 };
2175
2176 static inline u64 RVU_VF_INT_W1S(void)
2177 __attribute__ ((pure, always_inline));
RVU_VF_INT_W1S(void)2178 static inline u64 RVU_VF_INT_W1S(void)
2179 {
2180 return 0x28;
2181 }
2182
2183 /**
2184 * Register (RVU_VF_BAR2) rvu_vf_msix_pba#
2185 *
2186 * RVU VF MSI-X Pending-Bit-Array Registers This register is the MSI-X VF
2187 * PBA table.
2188 */
2189 union rvu_vf_msix_pbax {
2190 u64 u;
2191 struct rvu_vf_msix_pbax_s {
2192 u64 pend : 64;
2193 } s;
2194 /* struct rvu_vf_msix_pbax_s cn; */
2195 };
2196
2197 static inline u64 RVU_VF_MSIX_PBAX(u64 a)
2198 __attribute__ ((pure, always_inline));
RVU_VF_MSIX_PBAX(u64 a)2199 static inline u64 RVU_VF_MSIX_PBAX(u64 a)
2200 {
2201 return 0xf0000 + 8 * a;
2202 }
2203
2204 /**
2205 * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_addr
2206 *
2207 * RVU VF MSI-X Vector-Table Address Registers These registers and
2208 * RVU_VF_MSIX_VEC()_CTL form the VF MSI-X vector table. The number of
2209 * MSI-X vectors for a given VF is specified by
2210 * RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1] (plus 1). Software must do a
2211 * read after any writes to the MSI-X vector table to ensure that the
2212 * writes have completed before interrupts are generated to the modified
2213 * vectors.
2214 */
2215 union rvu_vf_msix_vecx_addr {
2216 u64 u;
2217 struct rvu_vf_msix_vecx_addr_s {
2218 u64 secvec : 1;
2219 u64 reserved_1 : 1;
2220 u64 addr : 51;
2221 u64 reserved_53_63 : 11;
2222 } s;
2223 /* struct rvu_vf_msix_vecx_addr_s cn; */
2224 };
2225
2226 static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a)
2227 __attribute__ ((pure, always_inline));
RVU_VF_MSIX_VECX_ADDR(u64 a)2228 static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a)
2229 {
2230 return 0x80000 + 0x10 * a;
2231 }
2232
2233 /**
2234 * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_ctl
2235 *
2236 * RVU VF MSI-X Vector-Table Control and Data Registers These registers
2237 * and RVU_VF_MSIX_VEC()_ADDR form the VF MSI-X vector table.
2238 */
2239 union rvu_vf_msix_vecx_ctl {
2240 u64 u;
2241 struct rvu_vf_msix_vecx_ctl_s {
2242 u64 data : 32;
2243 u64 mask : 1;
2244 u64 reserved_33_63 : 31;
2245 } s;
2246 /* struct rvu_vf_msix_vecx_ctl_s cn; */
2247 };
2248
2249 static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a)
2250 __attribute__ ((pure, always_inline));
RVU_VF_MSIX_VECX_CTL(u64 a)2251 static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a)
2252 {
2253 return 0x80008 + 0x10 * a;
2254 }
2255
2256 /**
2257 * Register (RVU_VF_BAR2) rvu_vf_vfpf_mbox#
2258 *
2259 * RVU VF/PF Mailbox Registers
2260 */
2261 union rvu_vf_vfpf_mboxx {
2262 u64 u;
2263 struct rvu_vf_vfpf_mboxx_s {
2264 u64 data : 64;
2265 } s;
2266 /* struct rvu_vf_vfpf_mboxx_s cn; */
2267 };
2268
2269 static inline u64 RVU_VF_VFPF_MBOXX(u64 a)
2270 __attribute__ ((pure, always_inline));
RVU_VF_VFPF_MBOXX(u64 a)2271 static inline u64 RVU_VF_VFPF_MBOXX(u64 a)
2272 {
2273 return 0 + 8 * a;
2274 }
2275
2276 #endif /* __CSRS_RVU_H__ */
2277