1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2011 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * Tom Cubie <tangliang@allwinnertech.com> 6 */ 7 8 #ifndef _SUNXI_CPU_SUN4I_H 9 #define _SUNXI_CPU_SUN4I_H 10 11 #define SUNXI_SRAM_A1_BASE 0x00000000 12 #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 13 14 #if defined(CONFIG_SUNXI_GEN_SUN6I) && \ 15 !defined(CONFIG_MACH_SUN8I_R40) && \ 16 !defined(CONFIG_MACH_SUN8I_V3S) 17 #define SUNXI_SRAM_A2_BASE 0x00040000 18 #ifdef CONFIG_MACH_SUN8I_H3 19 #define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */ 20 #else 21 #define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */ 22 #endif 23 #else 24 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 25 #endif 26 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 27 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 28 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 29 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 30 31 #define SUNXI_DE2_BASE 0x01000000 32 33 #ifdef CONFIG_MACH_SUN8I_A83T 34 #define SUNXI_CPUCFG_BASE 0x01700000 35 #endif 36 37 #define SUNXI_SRAMC_BASE 0x01c00000 38 #define SUNXI_DRAMC_BASE 0x01c01000 39 #define SUNXI_DMA_BASE 0x01c02000 40 #define SUNXI_NFC_BASE 0x01c03000 41 #define SUNXI_TS_BASE 0x01c04000 42 #define SUNXI_SPI0_BASE 0x01c05000 43 #define SUNXI_SPI1_BASE 0x01c06000 44 #define SUNXI_MS_BASE 0x01c07000 45 #define SUNXI_TVD_BASE 0x01c08000 46 #define SUNXI_CSI0_BASE 0x01c09000 47 #ifndef CONFIG_MACH_SUNXI_H3_H5 48 #define SUNXI_TVE0_BASE 0x01c0a000 49 #endif 50 #define SUNXI_EMAC_BASE 0x01c0b000 51 #define SUNXI_LCD0_BASE 0x01c0C000 52 #define SUNXI_LCD1_BASE 0x01c0d000 53 #define SUNXI_VE_BASE 0x01c0e000 54 #define SUNXI_MMC0_BASE 0x01c0f000 55 #define SUNXI_MMC1_BASE 0x01c10000 56 #define SUNXI_MMC2_BASE 0x01c11000 57 #define SUNXI_MMC3_BASE 0x01c12000 58 #ifdef CONFIG_SUNXI_GEN_SUN4I 59 #define SUNXI_USB0_BASE 0x01c13000 60 #define SUNXI_USB1_BASE 0x01c14000 61 #endif 62 #define SUNXI_SS_BASE 0x01c15000 63 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 64 #define SUNXI_HDMI_BASE 0x01c16000 65 #endif 66 #define SUNXI_SPI2_BASE 0x01c17000 67 #define SUNXI_SATA_BASE 0x01c18000 68 #ifdef CONFIG_SUNXI_GEN_SUN4I 69 #define SUNXI_PATA_BASE 0x01c19000 70 #define SUNXI_ACE_BASE 0x01c1a000 71 #define SUNXI_TVE1_BASE 0x01c1b000 72 #define SUNXI_USB2_BASE 0x01c1c000 73 #endif 74 #ifdef CONFIG_SUNXI_GEN_SUN6I 75 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 76 #define SUNXI_USBPHY_BASE 0x01c19000 77 #define SUNXI_USB0_BASE SUNXI_USBPHY_BASE 78 #define SUNXI_USB1_BASE 0x01c1a000 79 #define SUNXI_USB2_BASE 0x01c1b000 80 #define SUNXI_USB3_BASE 0x01c1c000 81 #define SUNXI_USB4_BASE 0x01c1d000 82 #else 83 #define SUNXI_USB0_BASE 0x01c19000 84 #define SUNXI_USB1_BASE 0x01c1a000 85 #define SUNXI_USB2_BASE 0x01c1b000 86 #endif 87 #endif 88 #define SUNXI_CSI1_BASE 0x01c1d000 89 #define SUNXI_TZASC_BASE 0x01c1e000 90 #define SUNXI_SPI3_BASE 0x01c1f000 91 92 #define SUNXI_CCM_BASE 0x01c20000 93 #define SUNXI_INTC_BASE 0x01c20400 94 #define SUNXI_PIO_BASE 0x01c20800 95 #define SUNXI_TIMER_BASE 0x01c20c00 96 #ifndef CONFIG_SUNXI_GEN_SUN6I 97 #define SUNXI_PWM_BASE 0x01c20e00 98 #endif 99 #define SUNXI_SPDIF_BASE 0x01c21000 100 #ifdef CONFIG_SUNXI_GEN_SUN6I 101 #define SUNXI_PWM_BASE 0x01c21400 102 #else 103 #define SUNXI_AC97_BASE 0x01c21400 104 #endif 105 #define SUNXI_IR0_BASE 0x01c21800 106 #define SUNXI_IR1_BASE 0x01c21c00 107 108 #define SUNXI_IIS_BASE 0x01c22400 109 #define SUNXI_LRADC_BASE 0x01c22800 110 #define SUNXI_AD_DA_BASE 0x01c22c00 111 #define SUNXI_KEYPAD_BASE 0x01c23000 112 #define SUNXI_TZPC_BASE 0x01c23400 113 114 #if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ 115 defined(CONFIG_MACH_SUN50I) 116 /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 117 #define SUNXI_SIDC_BASE 0x01c14000 118 #define SUNXI_SID_BASE 0x01c14200 119 #else 120 #define SUNXI_SID_BASE 0x01c23800 121 #endif 122 123 #define SUNXI_SJTAG_BASE 0x01c23c00 124 125 #define SUNXI_TP_BASE 0x01c25000 126 #define SUNXI_PMU_BASE 0x01c25400 127 128 #if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 129 #define SUNXI_CPUCFG_BASE 0x01c25c00 130 #endif 131 132 #define SUNXI_UART0_BASE 0x01c28000 133 #define SUNXI_UART1_BASE 0x01c28400 134 #define SUNXI_UART2_BASE 0x01c28800 135 #define SUNXI_UART3_BASE 0x01c28c00 136 #define SUNXI_UART4_BASE 0x01c29000 137 #define SUNXI_UART5_BASE 0x01c29400 138 #define SUNXI_UART6_BASE 0x01c29800 139 #define SUNXI_UART7_BASE 0x01c29c00 140 #define SUNXI_PS2_0_BASE 0x01c2a000 141 #define SUNXI_PS2_1_BASE 0x01c2a400 142 143 #define SUNXI_TWI0_BASE 0x01c2ac00 144 #define SUNXI_TWI1_BASE 0x01c2b000 145 #define SUNXI_TWI2_BASE 0x01c2b400 146 #ifdef CONFIG_MACH_SUN6I 147 #define SUNXI_TWI3_BASE 0x01c0b800 148 #endif 149 #ifdef CONFIG_MACH_SUN7I 150 #define SUNXI_TWI3_BASE 0x01c2b800 151 #define SUNXI_TWI4_BASE 0x01c2c000 152 #endif 153 154 #define SUNXI_CAN_BASE 0x01c2bc00 155 156 #define SUNXI_SCR_BASE 0x01c2c400 157 158 #ifndef CONFIG_MACH_SUN6I 159 #define SUNXI_GPS_BASE 0x01c30000 160 #define SUNXI_MALI400_BASE 0x01c40000 161 #define SUNXI_GMAC_BASE 0x01c50000 162 #else 163 #define SUNXI_GMAC_BASE 0x01c30000 164 #endif 165 166 #define SUNXI_DRAM_COM_BASE 0x01c62000 167 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 168 #define SUNXI_DRAM_CTL1_BASE 0x01c64000 169 #define SUNXI_DRAM_PHY0_BASE 0x01c65000 170 #define SUNXI_DRAM_PHY1_BASE 0x01c66000 171 172 #define SUNXI_GIC400_BASE 0x01c80000 173 174 /* module sram */ 175 #define SUNXI_SRAM_C_BASE 0x01d00000 176 177 #ifndef CONFIG_MACH_SUN8I_H3 178 #define SUNXI_DE_FE0_BASE 0x01e00000 179 #else 180 #define SUNXI_TVE0_BASE 0x01e00000 181 #endif 182 #define SUNXI_DE_FE1_BASE 0x01e20000 183 #define SUNXI_DE_BE0_BASE 0x01e60000 184 #ifndef CONFIG_MACH_SUN50I_H5 185 #define SUNXI_DE_BE1_BASE 0x01e40000 186 #else 187 #define SUNXI_TVE0_BASE 0x01e40000 188 #endif 189 #define SUNXI_MP_BASE 0x01e80000 190 #define SUNXI_AVG_BASE 0x01ea0000 191 192 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 193 #define SUNXI_HDMI_BASE 0x01ee0000 194 #endif 195 196 #define SUNXI_RTC_BASE 0x01f00000 197 #define SUNXI_PRCM_BASE 0x01f01400 198 199 #if defined CONFIG_SUNXI_GEN_SUN6I && \ 200 !defined CONFIG_MACH_SUN8I_A83T && \ 201 !defined CONFIG_MACH_SUN8I_R40 202 #define SUNXI_CPUCFG_BASE 0x01f01c00 203 #endif 204 205 #define SUNXI_R_TWI_BASE 0x01f02400 206 #define SUNXI_R_UART_BASE 0x01f02800 207 #define SUNXI_R_PIO_BASE 0x01f02c00 208 #define SUN6I_P2WI_BASE 0x01f03400 209 #define SUNXI_RSB_BASE 0x01f03400 210 211 /* CoreSight Debug Module */ 212 #define SUNXI_CSDM_BASE 0x3f500000 213 214 #define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 215 216 #define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 217 218 #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 219 220 /* SS bonding ids used for cpu identification */ 221 #define SUNXI_SS_BOND_ID_A31 4 222 #define SUNXI_SS_BOND_ID_A31S 5 223 224 #ifndef __ASSEMBLY__ 225 void sunxi_board_init(void); 226 void sunxi_reset(void); 227 int sunxi_get_ss_bonding_id(void); 228 int sunxi_get_sid(unsigned int *sid); 229 #endif /* __ASSEMBLY__ */ 230 231 #endif /* _SUNXI_CPU_SUN4I_H */ 232