1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2002-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #ifndef __ASM_GBL_DATA_H 8 #define __ASM_GBL_DATA_H 9 10 #ifndef __ASSEMBLY__ 11 12 #include <config.h> 13 14 #include <asm/types.h> 15 #include <linux/types.h> 16 17 /* Architecture-specific global data */ 18 struct arch_global_data { 19 #if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX) 20 u32 sdhc_clk; 21 #endif 22 23 #if defined(CONFIG_FSL_ESDHC) 24 u32 sdhc_per_clk; 25 #endif 26 27 #if defined(CONFIG_U_QE) 28 u32 qe_clk; 29 u32 brg_clk; 30 uint mp_alloc_base; 31 uint mp_alloc_top; 32 #endif /* CONFIG_U_QE */ 33 34 #ifdef CONFIG_AT91FAMILY 35 /* "static data" needed by at91's clock.c */ 36 unsigned long cpu_clk_rate_hz; 37 unsigned long main_clk_rate_hz; 38 unsigned long mck_rate_hz; 39 unsigned long plla_rate_hz; 40 unsigned long pllb_rate_hz; 41 unsigned long at91_pllb_usb_init; 42 #endif 43 /* "static data" needed by most of timer.c on ARM platforms */ 44 unsigned long timer_rate_hz; 45 unsigned int tbu; 46 unsigned int tbl; 47 unsigned long lastinc; 48 unsigned long long timer_reset_value; 49 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) 50 unsigned long tlb_addr; 51 unsigned long tlb_size; 52 #if defined(CONFIG_ARM64) 53 unsigned long tlb_fillptr; 54 unsigned long tlb_emerg; 55 #endif 56 #endif 57 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 58 #define MEM_RESERVE_SECURE_SECURED 0x1 59 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 60 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) 61 /* 62 * Secure memory addr 63 * This variable needs maintenance if the RAM base is not zero, 64 * or if RAM splits into non-consecutive banks. It also has a 65 * flag indicating the secure memory is marked as secure by MMU. 66 * Flags used: 0x1 secured 67 * 0x2 maintained 68 */ 69 phys_addr_t secure_ram; 70 unsigned long tlb_allocated; 71 #endif 72 #ifdef CONFIG_RESV_RAM 73 /* 74 * Reserved RAM for memory resident, eg. Management Complex (MC) 75 * driver which continues to run after U-Boot exits. 76 */ 77 phys_addr_t resv_ram; 78 #endif 79 80 #ifdef CONFIG_ARCH_OMAP2PLUS 81 u32 omap_boot_device; 82 u32 omap_boot_mode; 83 u8 omap_ch_flags; 84 #endif 85 #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) 86 unsigned long mem2_clk; 87 #endif 88 89 #ifdef CONFIG_ARCH_IMX8 90 struct udevice *scu_dev; 91 #endif 92 93 #ifdef CONFIG_ARCH_IMX8ULP 94 struct udevice *s400_dev; 95 #endif 96 97 }; 98 99 #include <asm-generic/global_data.h> 100 101 #if defined(__clang__) || defined(CONFIG_LTO) 102 103 #define DECLARE_GLOBAL_DATA_PTR 104 #define gd get_gd() 105 get_gd(void)106static inline gd_t *get_gd(void) 107 { 108 gd_t *gd_ptr; 109 110 #ifdef CONFIG_ARM64 111 __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); 112 #else 113 __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); 114 #endif 115 116 return gd_ptr; 117 } 118 119 #else 120 121 #ifdef CONFIG_ARM64 122 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") 123 #else 124 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") 125 #endif 126 #endif 127 set_gd(volatile gd_t * gd_ptr)128static inline void set_gd(volatile gd_t *gd_ptr) 129 { 130 #ifdef CONFIG_ARM64 131 __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr)); 132 #elif __ARM_ARCH >= 7 133 __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr)); 134 #else 135 __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr)); 136 #endif 137 } 138 139 #endif /* __ASSEMBLY__ */ 140 141 #endif /* __ASM_GBL_DATA_H */ 142