1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
3
4 #include <linux/compiler.h>
5 #include <asm/barriers.h>
6
7 #ifdef CONFIG_ARM64
8
9 /*
10 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
11 */
12 #define CR_M (1 << 0) /* MMU enable */
13 #define CR_A (1 << 1) /* Alignment abort enable */
14 #define CR_C (1 << 2) /* Dcache enable */
15 #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
16 #define CR_I (1 << 12) /* Icache enable */
17 #define CR_WXN (1 << 19) /* Write Permision Imply XN */
18 #define CR_EE (1 << 25) /* Exception (Big) Endian */
19
20 #define ES_TO_AARCH64 1
21 #define ES_TO_AARCH32 0
22
23 /*
24 * SCR_EL3 bits definitions
25 */
26 #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
27 #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
28 #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
29 #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
30 #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
31 #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */
32 #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
33
34 /*
35 * SPSR_EL3/SPSR_EL2 bits definitions
36 */
37 #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
38 #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
39 #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
40 #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
41 #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
42 #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
43 #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
44 #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
45 #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
46 #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
47 #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
48 #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
49 #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
50
51 /*
52 * CPTR_EL2 bits definitions
53 */
54 #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
55
56 /*
57 * SCTLR_EL2 bits definitions
58 */
59 #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
60 1 << 11 | 3 << 4) /* Reserved, RES1 */
61 #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
62 #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
63 #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
64 #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
65 #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
66 #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
67 #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
68
69 /*
70 * CNTHCTL_EL2 bits definitions
71 */
72 #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
73 #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
74
75 /*
76 * HCR_EL2 bits definitions
77 */
78 #define HCR_EL2_API (1 << 41) /* Trap pointer authentication
79 instructions */
80 #define HCR_EL2_APK (1 << 40) /* Trap pointer authentication
81 key access */
82 #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
83 #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
84 #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
85
86 /*
87 * ID_AA64ISAR1_EL1 bits definitions
88 */
89 #define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic
90 code auth algorithm */
91 #define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth
92 algorithm */
93 #define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address
94 auth algorithm */
95 #define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */
96
97 /*
98 * ID_AA64PFR0_EL1 bits definitions
99 */
100 #define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */
101 #define ID_AA64PFR0_EL1_EL2 (0xF << 8) /* EL2 implemented */
102
103 /*
104 * CPACR_EL1 bits definitions
105 */
106 #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
107
108 /*
109 * SCTLR_EL1 bits definitions
110 */
111 #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
112 1 << 11) /* Reserved, RES1 */
113 #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
114 #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
115 #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
116 #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
117 #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
118 #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
119 #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
120 #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
121 #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
122 #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
123 #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
124 #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
125 #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
126 #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
127 #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
128 #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
129 #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
130
131 #ifndef __ASSEMBLY__
132
133 struct pt_regs;
134
135 u64 get_page_table_size(void);
136 #define PGTABLE_SIZE get_page_table_size()
137
138 /* 2MB granularity */
139 #define MMU_SECTION_SHIFT 21
140 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
141
142 /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
143 enum dcache_option {
144 DCACHE_OFF = 0 << 2,
145 DCACHE_WRITETHROUGH = 3 << 2,
146 DCACHE_WRITEBACK = 4 << 2,
147 DCACHE_WRITEALLOC = 4 << 2,
148 };
149
150 #define wfi() \
151 ({asm volatile( \
152 "wfi" : : : "memory"); \
153 })
154
current_el(void)155 static inline unsigned int current_el(void)
156 {
157 unsigned long el;
158
159 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
160 return 3 & (el >> 2);
161 }
162
get_sctlr(void)163 static inline unsigned int get_sctlr(void)
164 {
165 unsigned int el;
166 unsigned long val;
167
168 el = current_el();
169 if (el == 1)
170 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
171 else if (el == 2)
172 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
173 else
174 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
175
176 return val;
177 }
178
set_sctlr(unsigned long val)179 static inline void set_sctlr(unsigned long val)
180 {
181 unsigned int el;
182
183 el = current_el();
184 if (el == 1)
185 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
186 else if (el == 2)
187 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
188 else
189 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
190
191 asm volatile("isb");
192 }
193
read_mpidr(void)194 static inline unsigned long read_mpidr(void)
195 {
196 unsigned long val;
197
198 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
199
200 return val;
201 }
202
203 #define BSP_COREID 0
204
205 void __asm_flush_dcache_all(void);
206 void __asm_invalidate_dcache_all(void);
207 void __asm_flush_dcache_range(u64 start, u64 end);
208
209 /**
210 * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
211 *
212 * This performance an invalidate from @start to @end - 1. Both addresses
213 * should be cache-aligned, otherwise this function will align the start
214 * address and may continue past the end address.
215 *
216 * Data in the address range is evicted from the cache and is not written back
217 * to memory.
218 *
219 * @start: Start address to invalidate
220 * @end: End address to invalidate up to (exclusive)
221 */
222 void __asm_invalidate_dcache_range(u64 start, u64 end);
223 void __asm_invalidate_tlb_all(void);
224 void __asm_invalidate_icache_all(void);
225 int __asm_invalidate_l3_dcache(void);
226 int __asm_flush_l3_dcache(void);
227 int __asm_invalidate_l3_icache(void);
228 void __asm_switch_ttbr(u64 new_ttbr);
229
230 /*
231 * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
232 *
233 * @args: For loading 64-bit OS, fdt address.
234 * For loading 32-bit OS, zero.
235 * @mach_nr: For loading 64-bit OS, zero.
236 * For loading 32-bit OS, machine nr
237 * @fdt_addr: For loading 64-bit OS, zero.
238 * For loading 32-bit OS, fdt address.
239 * @arg4: Input argument.
240 * @entry_point: kernel entry point
241 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
242 */
243 void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
244 u64 arg4, u64 entry_point, u64 es_flag);
245 /*
246 * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
247 *
248 * @args: For loading 64-bit OS, fdt address.
249 * For loading 32-bit OS, zero.
250 * @mach_nr: For loading 64-bit OS, zero.
251 * For loading 32-bit OS, machine nr
252 * @fdt_addr: For loading 64-bit OS, zero.
253 * For loading 32-bit OS, fdt address.
254 * @arg4: Input argument.
255 * @entry_point: kernel entry point
256 * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
257 */
258 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
259 u64 arg4, u64 entry_point, u64 es_flag);
260 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
261 u64 arg4, u64 entry_point);
262 void gic_init(void);
263 void gic_send_sgi(unsigned long sgino);
264 void wait_for_wakeup(void);
265 void protect_secure_region(void);
266 void smp_kick_all_cpus(void);
267
268 void flush_l3_cache(void);
269 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
270
271 /*
272 * smc_call() - issue a secure monitor call
273 *
274 * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
275 * DEN0028A
276 *
277 * @args: input and output arguments
278 */
279 void smc_call(struct pt_regs *args);
280
281 void __noreturn psci_system_reset(void);
282 void __noreturn psci_system_reset2(u32 reset_level, u32 cookie);
283 void __noreturn psci_system_off(void);
284
285 #ifdef CONFIG_ARMV8_PSCI
286 extern char __secure_start[];
287 extern char __secure_end[];
288 extern char __secure_stack_start[];
289 extern char __secure_stack_end[];
290
291 void armv8_setup_psci(void);
292 void psci_setup_vectors(void);
293 void psci_arch_init(void);
294 #endif
295
296 #endif /* __ASSEMBLY__ */
297
298 #else /* CONFIG_ARM64 */
299
300 #ifdef __KERNEL__
301
302 #define CPU_ARCH_UNKNOWN 0
303 #define CPU_ARCH_ARMv3 1
304 #define CPU_ARCH_ARMv4 2
305 #define CPU_ARCH_ARMv4T 3
306 #define CPU_ARCH_ARMv5 4
307 #define CPU_ARCH_ARMv5T 5
308 #define CPU_ARCH_ARMv5TE 6
309 #define CPU_ARCH_ARMv5TEJ 7
310 #define CPU_ARCH_ARMv6 8
311 #define CPU_ARCH_ARMv7 9
312
313 /*
314 * CR1 bits (CP#15 CR1)
315 */
316 #define CR_M (1 << 0) /* MMU enable */
317 #define CR_A (1 << 1) /* Alignment abort enable */
318 #define CR_C (1 << 2) /* Dcache enable */
319 #define CR_W (1 << 3) /* Write buffer enable */
320 #define CR_P (1 << 4) /* 32-bit exception handler */
321 #define CR_D (1 << 5) /* 32-bit data address range */
322 #define CR_L (1 << 6) /* Implementation defined */
323 #define CR_B (1 << 7) /* Big endian */
324 #define CR_S (1 << 8) /* System MMU protection */
325 #define CR_R (1 << 9) /* ROM MMU protection */
326 #define CR_F (1 << 10) /* Implementation defined */
327 #define CR_Z (1 << 11) /* Implementation defined */
328 #define CR_I (1 << 12) /* Icache enable */
329 #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
330 #define CR_RR (1 << 14) /* Round Robin cache replacement */
331 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
332 #define CR_DT (1 << 16)
333 #define CR_IT (1 << 18)
334 #define CR_ST (1 << 19)
335 #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
336 #define CR_U (1 << 22) /* Unaligned access operation */
337 #define CR_XP (1 << 23) /* Extended page tables */
338 #define CR_VE (1 << 24) /* Vectored interrupts */
339 #define CR_EE (1 << 25) /* Exception (Big) Endian */
340 #define CR_TRE (1 << 28) /* TEX remap enable */
341 #define CR_AFE (1 << 29) /* Access flag enable */
342 #define CR_TE (1 << 30) /* Thumb exception enable */
343
344 #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
345 #define PGTABLE_SIZE (4096 * 5)
346 #elif !defined(PGTABLE_SIZE)
347 #define PGTABLE_SIZE (4096 * 4)
348 #endif
349
350 /*
351 * This is used to ensure the compiler did actually allocate the register we
352 * asked it for some inline assembly sequences. Apparently we can't trust
353 * the compiler from one version to another so a bit of paranoia won't hurt.
354 * This string is meant to be concatenated with the inline asm string and
355 * will cause compilation to stop on mismatch.
356 * (for details, see gcc PR 15089)
357 */
358 #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
359
360 #ifndef __ASSEMBLY__
361
362 #ifdef CONFIG_ARMV7_LPAE
363 void switch_to_hypervisor_ret(void);
364 #endif
365
366 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
367
368 #ifdef __ARM_ARCH_7A__
369 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
370 #else
371 #define wfi()
372 #endif
373
get_cpsr(void)374 static inline unsigned long get_cpsr(void)
375 {
376 unsigned long cpsr;
377
378 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
379 return cpsr;
380 }
381
is_hyp(void)382 static inline int is_hyp(void)
383 {
384 #ifdef CONFIG_ARMV7_LPAE
385 /* HYP mode requires LPAE ... */
386 return ((get_cpsr() & 0x1f) == 0x1a);
387 #else
388 /* ... so without LPAE support we can optimize all hyp code away */
389 return 0;
390 #endif
391 }
392
get_cr(void)393 static inline unsigned int get_cr(void)
394 {
395 unsigned int val;
396
397 if (is_hyp())
398 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
399 :
400 : "cc");
401 else
402 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
403 :
404 : "cc");
405 return val;
406 }
407
set_cr(unsigned int val)408 static inline void set_cr(unsigned int val)
409 {
410 if (is_hyp())
411 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
412 : "r" (val)
413 : "cc");
414 else
415 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
416 : "r" (val)
417 : "cc");
418 isb();
419 }
420
421 #ifdef CONFIG_ARMV7_LPAE
422 /* Long-Descriptor Translation Table Level 1/2 Bits */
423 #define TTB_SECT_XN_MASK (1ULL << 54)
424 #define TTB_SECT_NG_MASK (1 << 11)
425 #define TTB_SECT_AF (1 << 10)
426 #define TTB_SECT_SH_MASK (3 << 8)
427 #define TTB_SECT_NS_MASK (1 << 5)
428 #define TTB_SECT_AP (1 << 6)
429 /* Note: TTB AP bits are set elsewhere */
430 #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
431 #define TTB_SECT (1 << 0)
432 #define TTB_PAGETABLE (3 << 0)
433
434 /* TTBCR flags */
435 #define TTBCR_EAE (1 << 31)
436 #define TTBCR_T0SZ(x) ((x) << 0)
437 #define TTBCR_T1SZ(x) ((x) << 16)
438 #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
439 #define TTBCR_IRGN0_NC (0 << 8)
440 #define TTBCR_IRGN0_WBWA (1 << 8)
441 #define TTBCR_IRGN0_WT (2 << 8)
442 #define TTBCR_IRGN0_WBNWA (3 << 8)
443 #define TTBCR_IRGN0_MASK (3 << 8)
444 #define TTBCR_ORGN0_NC (0 << 10)
445 #define TTBCR_ORGN0_WBWA (1 << 10)
446 #define TTBCR_ORGN0_WT (2 << 10)
447 #define TTBCR_ORGN0_WBNWA (3 << 10)
448 #define TTBCR_ORGN0_MASK (3 << 10)
449 #define TTBCR_SHARED_NON (0 << 12)
450 #define TTBCR_SHARED_OUTER (2 << 12)
451 #define TTBCR_SHARED_INNER (3 << 12)
452 #define TTBCR_EPD0 (0 << 7)
453
454 /*
455 * VMSAv8-32 Long-descriptor format memory region attributes
456 * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a])
457 *
458 * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered)
459 * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate
460 * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate
461 * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate
462 */
463 #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \
464 (0xee << (2 * 8)) | (0xff << (3 * 8)))
465
466 /* options available for data cache on each page */
467 enum dcache_option {
468 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
469 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
470 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
471 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
472 };
473 #elif defined(CONFIG_CPU_V7A)
474 /* Short-Descriptor Translation Table Level 1 Bits */
475 #define TTB_SECT_NS_MASK (1 << 19)
476 #define TTB_SECT_NG_MASK (1 << 17)
477 #define TTB_SECT_S_MASK (1 << 16)
478 /* Note: TTB AP bits are set elsewhere */
479 #define TTB_SECT_AP (3 << 10)
480 #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
481 #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
482 #define TTB_SECT_XN_MASK (1 << 4)
483 #define TTB_SECT_C_MASK (1 << 3)
484 #define TTB_SECT_B_MASK (1 << 2)
485 #define TTB_SECT (2 << 0)
486
487 /*
488 * Short-descriptor format memory region attributes, without TEX remap
489 * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a])
490 *
491 * TEX[0] C B
492 * 0 0 0 Device-nGnRnE (aka Strongly-Ordered)
493 * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate
494 * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate
495 * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate
496 */
497 enum dcache_option {
498 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
499 DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
500 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
501 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
502 };
503 #else
504 #define TTB_SECT_AP (3 << 10)
505 /* options available for data cache on each page */
506 enum dcache_option {
507 DCACHE_OFF = 0x12,
508 DCACHE_WRITETHROUGH = 0x1a,
509 DCACHE_WRITEBACK = 0x1e,
510 DCACHE_WRITEALLOC = 0x16,
511 };
512 #endif
513
514 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
515 #define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
516 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
517 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
518 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
519 #define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
520 #endif
521
522 /* Size of an MMU section */
523 enum {
524 #ifdef CONFIG_ARMV7_LPAE
525 MMU_SECTION_SHIFT = 21, /* 2MB */
526 #else
527 MMU_SECTION_SHIFT = 20, /* 1MB */
528 #endif
529 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
530 };
531
532 #ifdef CONFIG_CPU_V7A
533 /* TTBR0 bits */
534 #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
535 #define TTBR0_RGN_NC (0 << 3)
536 #define TTBR0_RGN_WBWA (1 << 3)
537 #define TTBR0_RGN_WT (2 << 3)
538 #define TTBR0_RGN_WB (3 << 3)
539 /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
540 #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
541 #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
542 #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
543 #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
544 #endif
545
546 /**
547 * mmu_page_table_flush() - register an update to page tables
548 *
549 * Register an update to the page tables, and flush the TLB
550 *
551 * @start: start address of update in page table
552 * @stop: stop address of update in page table
553 */
554 void mmu_page_table_flush(unsigned long start, unsigned long stop);
555
556 #ifdef CONFIG_ARMV7_PSCI
557 void psci_arch_cpu_entry(void);
558 void psci_arch_init(void);
559 u32 psci_version(void);
560 s32 psci_features(u32 function_id, u32 psci_fid);
561 s32 psci_cpu_off(void);
562 s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
563 u32 context_id);
564 s32 psci_affinity_info(u32 function_id, u32 target_affinity,
565 u32 lowest_affinity_level);
566 u32 psci_migrate_info_type(void);
567 void psci_system_off(void);
568 void psci_system_reset(void);
569 #endif
570
571 #endif /* __ASSEMBLY__ */
572
573 #define arch_align_stack(x) (x)
574
575 #endif /* __KERNEL__ */
576
577 #endif /* CONFIG_ARM64 */
578
579 #ifndef __ASSEMBLY__
580 /**
581 * save_boot_params() - Save boot parameters before starting reset sequence
582 *
583 * If you provide this function it will be called immediately U-Boot starts,
584 * both for SPL and U-Boot proper.
585 *
586 * All registers are unchanged from U-Boot entry. No registers need be
587 * preserved.
588 *
589 * This is not a normal C function. There is no stack. Return by branching to
590 * save_boot_params_ret.
591 *
592 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
593 */
594
595 /**
596 * save_boot_params_ret() - Return from save_boot_params()
597 *
598 * If you provide save_boot_params(), then you should jump back to this
599 * function when done. Try to preserve all registers.
600 *
601 * If your implementation of save_boot_params() is in C then it is acceptable
602 * to simply call save_boot_params_ret() at the end of your function. Since
603 * there is no link register set up, you cannot just exit the function. U-Boot
604 * will return to the (initialised) value of lr, and likely crash/hang.
605 *
606 * If your implementation of save_boot_params() is in assembler then you
607 * should use 'b' or 'bx' to return to save_boot_params_ret.
608 */
609 void save_boot_params_ret(void);
610
611 /**
612 * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
613 *
614 * Change the virt/phys mapping and cache settings for a region.
615 *
616 * @virt: virtual start address of memory region to change
617 * @phys: physical address for the memory region to set
618 * @size: size of memory region to change
619 * @option: dcache option to select
620 */
621 void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
622 size_t size, enum dcache_option option);
623
624 /**
625 * mmu_set_region_dcache_behaviour() - set cache settings
626 *
627 * Change the cache settings for a region.
628 *
629 * @start: start address of memory region to change
630 * @size: size of memory region to change
631 * @option: dcache option to select
632 */
633 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
634 enum dcache_option option);
635
636 #ifdef CONFIG_SYS_NONCACHED_MEMORY
637 /**
638 * noncached_init() - Initialize non-cached memory region
639 *
640 * Initialize non-cached memory area. This memory region will be typically
641 * located right below the malloc() area and mapped uncached in the MMU.
642 *
643 * It is called during the generic post-relocation init sequence.
644 *
645 * Return: 0 if OK
646 */
647 int noncached_init(void);
648
649 phys_addr_t noncached_alloc(size_t size, size_t align);
650 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
651
652 #endif /* __ASSEMBLY__ */
653
654 #endif
655