1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/io.h>
13 #include <asm/arch/sys_proto.h>
14 #include <errno.h>
15 #include <linux/delay.h>
16 #include <linux/iopoll.h>
17
18 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
19
20 static u32 get_root_clk(enum clk_root_index clock_id);
21
decode_frac_pll(enum clk_root_src frac_pll)22 static u32 decode_frac_pll(enum clk_root_src frac_pll)
23 {
24 u32 pll_cfg0, pll_cfg1, pllout;
25 u32 pll_refclk_sel, pll_refclk;
26 u32 divr_val, divq_val, divf_val, divff, divfi;
27 u32 pllout_div_shift, pllout_div_mask, pllout_div;
28
29 switch (frac_pll) {
30 case ARM_PLL_CLK:
31 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
33 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
34 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
35 break;
36 default:
37 printf("Frac PLL %d not supporte\n", frac_pll);
38 return 0;
39 }
40
41 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
42 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
43
44 /* Power down */
45 if (pll_cfg0 & FRAC_PLL_PD_MASK)
46 return 0;
47
48 /* output not enabled */
49 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
50 return 0;
51
52 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
53
54 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
55 pll_refclk = 25000000u;
56 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
57 pll_refclk = 27000000u;
58 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
59 pll_refclk = 27000000u;
60 else
61 pll_refclk = 0;
62
63 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
64 return pll_refclk;
65
66 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
67 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
68 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
69
70 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
71 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
73
74 divf_val = 1 + divfi + divff / (1 << 24);
75
76 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
77 ((divq_val + 1) * 2);
78
79 return pllout / (pllout_div + 1);
80 }
81
decode_sscg_pll(enum clk_root_src sscg_pll)82 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
83 {
84 u32 pll_cfg0, pll_cfg1, pll_cfg2;
85 u32 pll_refclk_sel, pll_refclk;
86 u32 divr1, divr2, divf1, divf2, divq, div;
87 u32 sse;
88 u32 pll_clke;
89 u32 pllout_div_shift, pllout_div_mask, pllout_div;
90 u32 pllout;
91
92 switch (sscg_pll) {
93 case SYSTEM_PLL1_800M_CLK:
94 case SYSTEM_PLL1_400M_CLK:
95 case SYSTEM_PLL1_266M_CLK:
96 case SYSTEM_PLL1_200M_CLK:
97 case SYSTEM_PLL1_160M_CLK:
98 case SYSTEM_PLL1_133M_CLK:
99 case SYSTEM_PLL1_100M_CLK:
100 case SYSTEM_PLL1_80M_CLK:
101 case SYSTEM_PLL1_40M_CLK:
102 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
104 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
105 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
106 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
107 break;
108 case SYSTEM_PLL2_1000M_CLK:
109 case SYSTEM_PLL2_500M_CLK:
110 case SYSTEM_PLL2_333M_CLK:
111 case SYSTEM_PLL2_250M_CLK:
112 case SYSTEM_PLL2_200M_CLK:
113 case SYSTEM_PLL2_166M_CLK:
114 case SYSTEM_PLL2_125M_CLK:
115 case SYSTEM_PLL2_100M_CLK:
116 case SYSTEM_PLL2_50M_CLK:
117 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
119 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
120 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
121 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
122 break;
123 case SYSTEM_PLL3_CLK:
124 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
126 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
127 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
128 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
129 break;
130 case DRAM_PLL1_CLK:
131 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
133 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
134 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
135 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
136 break;
137 default:
138 printf("sscg pll %d not supporte\n", sscg_pll);
139 return 0;
140 }
141
142 switch (sscg_pll) {
143 case DRAM_PLL1_CLK:
144 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
145 div = 1;
146 break;
147 case SYSTEM_PLL3_CLK:
148 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
149 div = 1;
150 break;
151 case SYSTEM_PLL2_1000M_CLK:
152 case SYSTEM_PLL1_800M_CLK:
153 pll_clke = SSCG_PLL_CLKE_MASK;
154 div = 1;
155 break;
156 case SYSTEM_PLL2_500M_CLK:
157 case SYSTEM_PLL1_400M_CLK:
158 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
159 div = 2;
160 break;
161 case SYSTEM_PLL2_333M_CLK:
162 case SYSTEM_PLL1_266M_CLK:
163 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
164 div = 3;
165 break;
166 case SYSTEM_PLL2_250M_CLK:
167 case SYSTEM_PLL1_200M_CLK:
168 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
169 div = 4;
170 break;
171 case SYSTEM_PLL2_200M_CLK:
172 case SYSTEM_PLL1_160M_CLK:
173 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
174 div = 5;
175 break;
176 case SYSTEM_PLL2_166M_CLK:
177 case SYSTEM_PLL1_133M_CLK:
178 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
179 div = 6;
180 break;
181 case SYSTEM_PLL2_125M_CLK:
182 case SYSTEM_PLL1_100M_CLK:
183 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
184 div = 8;
185 break;
186 case SYSTEM_PLL2_100M_CLK:
187 case SYSTEM_PLL1_80M_CLK:
188 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
189 div = 10;
190 break;
191 case SYSTEM_PLL2_50M_CLK:
192 case SYSTEM_PLL1_40M_CLK:
193 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
194 div = 20;
195 break;
196 default:
197 printf("sscg pll %d not supporte\n", sscg_pll);
198 return 0;
199 }
200
201 /* Power down */
202 if (pll_cfg0 & SSCG_PLL_PD_MASK)
203 return 0;
204
205 /* output not enabled */
206 if ((pll_cfg0 & pll_clke) == 0)
207 return 0;
208
209 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
210 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
211
212 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
213
214 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
215 pll_refclk = 25000000u;
216 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
217 pll_refclk = 27000000u;
218 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
219 pll_refclk = 27000000u;
220 else
221 pll_refclk = 0;
222
223 /* We assume bypass1/2 are the same value */
224 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
225 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
226 return pll_refclk;
227
228 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
229 SSCG_PLL_REF_DIVR1_SHIFT;
230 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
231 SSCG_PLL_REF_DIVR2_SHIFT;
232 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
233 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
234 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
235 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
236 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
237 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
239
240 if (sse)
241 sse = 8;
242 else
243 sse = 2;
244
245 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
246 (divr2 + 1) * (divf2 + 1) / (divq + 1);
247
248 return pllout / (pllout_div + 1) / div;
249 }
250
get_root_src_clk(enum clk_root_src root_src)251 static u32 get_root_src_clk(enum clk_root_src root_src)
252 {
253 switch (root_src) {
254 case OSC_25M_CLK:
255 return 25000000;
256 case OSC_27M_CLK:
257 return 27000000;
258 case OSC_32K_CLK:
259 return 32768;
260 case ARM_PLL_CLK:
261 return decode_frac_pll(root_src);
262 case SYSTEM_PLL1_800M_CLK:
263 case SYSTEM_PLL1_400M_CLK:
264 case SYSTEM_PLL1_266M_CLK:
265 case SYSTEM_PLL1_200M_CLK:
266 case SYSTEM_PLL1_160M_CLK:
267 case SYSTEM_PLL1_133M_CLK:
268 case SYSTEM_PLL1_100M_CLK:
269 case SYSTEM_PLL1_80M_CLK:
270 case SYSTEM_PLL1_40M_CLK:
271 case SYSTEM_PLL2_1000M_CLK:
272 case SYSTEM_PLL2_500M_CLK:
273 case SYSTEM_PLL2_333M_CLK:
274 case SYSTEM_PLL2_250M_CLK:
275 case SYSTEM_PLL2_200M_CLK:
276 case SYSTEM_PLL2_166M_CLK:
277 case SYSTEM_PLL2_125M_CLK:
278 case SYSTEM_PLL2_100M_CLK:
279 case SYSTEM_PLL2_50M_CLK:
280 case SYSTEM_PLL3_CLK:
281 return decode_sscg_pll(root_src);
282 case ARM_A53_ALT_CLK:
283 return get_root_clk(ARM_A53_CLK_ROOT);
284 default:
285 return 0;
286 }
287
288 return 0;
289 }
290
get_root_clk(enum clk_root_index clock_id)291 static u32 get_root_clk(enum clk_root_index clock_id)
292 {
293 enum clk_root_src root_src;
294 u32 post_podf, pre_podf, root_src_clk;
295
296 if (clock_root_enabled(clock_id) <= 0)
297 return 0;
298
299 if (clock_get_prediv(clock_id, &pre_podf) < 0)
300 return 0;
301
302 if (clock_get_postdiv(clock_id, &post_podf) < 0)
303 return 0;
304
305 if (clock_get_src(clock_id, &root_src) < 0)
306 return 0;
307
308 root_src_clk = get_root_src_clk(root_src);
309
310 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
311 }
312
313 #ifdef CONFIG_IMX_HAB
hab_caam_clock_enable(unsigned char enable)314 void hab_caam_clock_enable(unsigned char enable)
315 {
316 /* The CAAM clock is always on for iMX8M */
317 }
318 #endif
319
320 #ifdef CONFIG_MXC_OCOTP
enable_ocotp_clk(unsigned char enable)321 void enable_ocotp_clk(unsigned char enable)
322 {
323 clock_enable(CCGR_OCOTP, !!enable);
324 }
325 #endif
326
enable_i2c_clk(unsigned char enable,unsigned int i2c_num)327 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
328 {
329 /* 0 - 3 is valid i2c num */
330 if (i2c_num > 3)
331 return -EINVAL;
332
333 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
334
335 return 0;
336 }
337
get_arm_core_clk(void)338 u32 get_arm_core_clk(void)
339 {
340 enum clk_root_src root_src;
341 u32 root_src_clk;
342
343 if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
344 return 0;
345
346 root_src_clk = get_root_src_clk(root_src);
347
348 return root_src_clk;
349 }
350
mxc_get_clock(enum mxc_clock clk)351 unsigned int mxc_get_clock(enum mxc_clock clk)
352 {
353 u32 val;
354
355 switch (clk) {
356 case MXC_ARM_CLK:
357 return get_arm_core_clk();
358 case MXC_IPG_CLK:
359 clock_get_target_val(IPG_CLK_ROOT, &val);
360 val = val & 0x3;
361 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
362 case MXC_ESDHC_CLK:
363 return get_root_clk(USDHC1_CLK_ROOT);
364 case MXC_ESDHC2_CLK:
365 return get_root_clk(USDHC2_CLK_ROOT);
366 default:
367 return get_root_clk(clk);
368 }
369 }
370
imx_get_uartclk(void)371 u32 imx_get_uartclk(void)
372 {
373 return mxc_get_clock(UART1_CLK_ROOT);
374 }
375
mxs_set_lcdclk(u32 base_addr,u32 freq)376 void mxs_set_lcdclk(u32 base_addr, u32 freq)
377 {
378 /*
379 * LCDIF_PIXEL_CLK: select 800MHz root clock,
380 * select pre divider 8, output is 100 MHz
381 */
382 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
383 CLK_ROOT_SOURCE_SEL(4) |
384 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
385 }
386
init_wdog_clk(void)387 void init_wdog_clk(void)
388 {
389 clock_enable(CCGR_WDOG1, 0);
390 clock_enable(CCGR_WDOG2, 0);
391 clock_enable(CCGR_WDOG3, 0);
392 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
393 CLK_ROOT_SOURCE_SEL(0));
394 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
395 CLK_ROOT_SOURCE_SEL(0));
396 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
397 CLK_ROOT_SOURCE_SEL(0));
398 clock_enable(CCGR_WDOG1, 1);
399 clock_enable(CCGR_WDOG2, 1);
400 clock_enable(CCGR_WDOG3, 1);
401 }
402
init_usb_clk(void)403 void init_usb_clk(void)
404 {
405 if (!is_usb_boot()) {
406 clock_enable(CCGR_USB_CTRL1, 0);
407 clock_enable(CCGR_USB_CTRL2, 0);
408 clock_enable(CCGR_USB_PHY1, 0);
409 clock_enable(CCGR_USB_PHY2, 0);
410 /* 500MHz */
411 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
412 CLK_ROOT_SOURCE_SEL(1));
413 /* 100MHz */
414 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
415 CLK_ROOT_SOURCE_SEL(1));
416 /* 100MHz */
417 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
418 CLK_ROOT_SOURCE_SEL(1));
419 clock_enable(CCGR_USB_CTRL1, 1);
420 clock_enable(CCGR_USB_CTRL2, 1);
421 clock_enable(CCGR_USB_PHY1, 1);
422 clock_enable(CCGR_USB_PHY2, 1);
423 }
424 }
425
init_nand_clk(void)426 void init_nand_clk(void)
427 {
428 clock_enable(CCGR_RAWNAND, 0);
429 clock_set_target_val(NAND_CLK_ROOT,
430 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
431 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
432 clock_enable(CCGR_RAWNAND, 1);
433 }
434
init_uart_clk(u32 index)435 void init_uart_clk(u32 index)
436 {
437 /* Set uart clock root 25M OSC */
438 switch (index) {
439 case 0:
440 clock_enable(CCGR_UART1, 0);
441 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
442 CLK_ROOT_SOURCE_SEL(0));
443 clock_enable(CCGR_UART1, 1);
444 return;
445 case 1:
446 clock_enable(CCGR_UART2, 0);
447 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
448 CLK_ROOT_SOURCE_SEL(0));
449 clock_enable(CCGR_UART2, 1);
450 return;
451 case 2:
452 clock_enable(CCGR_UART3, 0);
453 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
454 CLK_ROOT_SOURCE_SEL(0));
455 clock_enable(CCGR_UART3, 1);
456 return;
457 case 3:
458 clock_enable(CCGR_UART4, 0);
459 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
460 CLK_ROOT_SOURCE_SEL(0));
461 clock_enable(CCGR_UART4, 1);
462 return;
463 default:
464 printf("Invalid uart index\n");
465 return;
466 }
467 }
468
init_clk_usdhc(u32 index)469 void init_clk_usdhc(u32 index)
470 {
471 /*
472 * set usdhc clock root
473 * sys pll1 400M
474 */
475 switch (index) {
476 case 0:
477 clock_enable(CCGR_USDHC1, 0);
478 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
479 CLK_ROOT_SOURCE_SEL(1));
480 clock_enable(CCGR_USDHC1, 1);
481 return;
482 case 1:
483 clock_enable(CCGR_USDHC2, 0);
484 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
485 CLK_ROOT_SOURCE_SEL(1));
486 clock_enable(CCGR_USDHC2, 1);
487 return;
488 default:
489 printf("Invalid usdhc index\n");
490 return;
491 }
492 }
493
set_clk_qspi(void)494 int set_clk_qspi(void)
495 {
496 /*
497 * set qspi root
498 * sys pll1 100M
499 */
500 clock_enable(CCGR_QSPI, 0);
501 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
502 CLK_ROOT_SOURCE_SEL(7));
503 clock_enable(CCGR_QSPI, 1);
504
505 return 0;
506 }
507
508 #ifdef CONFIG_FEC_MXC
set_clk_enet(enum enet_freq type)509 int set_clk_enet(enum enet_freq type)
510 {
511 u32 target;
512 u32 enet1_ref;
513
514 switch (type) {
515 case ENET_125MHZ:
516 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
517 break;
518 case ENET_50MHZ:
519 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
520 break;
521 case ENET_25MHZ:
522 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 /* disable the clock first */
529 clock_enable(CCGR_ENET1, 0);
530 clock_enable(CCGR_SIM_ENET, 0);
531
532 /* set enet axi clock 266Mhz */
533 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
534 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
535 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
536 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
537
538 target = CLK_ROOT_ON | enet1_ref |
539 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
540 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
541 clock_set_target_val(ENET_REF_CLK_ROOT, target);
542
543 target = CLK_ROOT_ON |
544 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
545 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
546 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
547 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
548
549 /* enable clock */
550 clock_enable(CCGR_SIM_ENET, 1);
551 clock_enable(CCGR_ENET1, 1);
552
553 return 0;
554 }
555 #endif
556
imx_get_fecclk(void)557 u32 imx_get_fecclk(void)
558 {
559 return get_root_clk(ENET_AXI_CLK_ROOT);
560 }
561
562 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
563 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
564 CLK_ROOT_PRE_DIV2),
565 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
566 CLK_ROOT_PRE_DIV2),
567 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
568 CLK_ROOT_PRE_DIV2),
569 };
570
dram_enable_bypass(ulong clk_val)571 void dram_enable_bypass(ulong clk_val)
572 {
573 int i;
574 struct dram_bypass_clk_setting *config;
575
576 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
577 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
578 break;
579 }
580
581 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
582 printf("No matched freq table %lu\n", clk_val);
583 return;
584 }
585
586 config = &imx8mq_dram_bypass_tbl[i];
587
588 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
589 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
590 CLK_ROOT_PRE_DIV(config->alt_pre_div));
591 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
592 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
593 CLK_ROOT_PRE_DIV(config->apb_pre_div));
594 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
595 CLK_ROOT_SOURCE_SEL(1));
596 }
597
dram_disable_bypass(void)598 void dram_disable_bypass(void)
599 {
600 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
601 CLK_ROOT_SOURCE_SEL(0));
602 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
603 CLK_ROOT_SOURCE_SEL(4) |
604 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
605 }
606
607 #ifdef CONFIG_SPL_BUILD
dram_pll_init(ulong pll_val)608 void dram_pll_init(ulong pll_val)
609 {
610 u32 val;
611 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
612 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
613
614 /* Bypass */
615 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
616 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
617
618 switch (pll_val) {
619 case MHZ(800):
620 val = readl(pll_cfg_reg2);
621 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
622 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
623 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
624 SSCG_PLL_REF_DIVR2_MASK);
625 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
626 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
627 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
628 val |= SSCG_PLL_REF_DIVR2_VAL(29);
629 writel(val, pll_cfg_reg2);
630 break;
631 case MHZ(600):
632 val = readl(pll_cfg_reg2);
633 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
634 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
635 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
636 SSCG_PLL_REF_DIVR2_MASK);
637 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
638 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
639 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
640 val |= SSCG_PLL_REF_DIVR2_VAL(29);
641 writel(val, pll_cfg_reg2);
642 break;
643 case MHZ(400):
644 val = readl(pll_cfg_reg2);
645 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
646 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
647 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
648 SSCG_PLL_REF_DIVR2_MASK);
649 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
650 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
651 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
652 val |= SSCG_PLL_REF_DIVR2_VAL(29);
653 writel(val, pll_cfg_reg2);
654 break;
655 case MHZ(167):
656 val = readl(pll_cfg_reg2);
657 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
658 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
659 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
660 SSCG_PLL_REF_DIVR2_MASK);
661 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
662 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
663 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
664 val |= SSCG_PLL_REF_DIVR2_VAL(30);
665 writel(val, pll_cfg_reg2);
666 break;
667 default:
668 break;
669 }
670
671 /* Clear power down bit */
672 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
673 /* Eanble ARM_PLL/SYS_PLL */
674 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
675
676 /* Clear bypass */
677 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
678 __udelay(100);
679 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
680 /* Wait lock */
681 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
682 ;
683 }
684
frac_pll_init(u32 pll,enum frac_pll_out_val val)685 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
686 {
687 void __iomem *pll_cfg0, __iomem *pll_cfg1;
688 u32 val_cfg0, val_cfg1, divq;
689 int ret;
690
691 switch (pll) {
692 case ANATOP_ARM_PLL:
693 pll_cfg0 = &ana_pll->arm_pll_cfg0;
694 pll_cfg1 = &ana_pll->arm_pll_cfg1;
695
696 if (val == FRAC_PLL_OUT_1000M) {
697 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
698 divq = 0;
699 } else {
700 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
701 divq = 1;
702 }
703 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
704 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
705 FRAC_PLL_REFCLK_DIV_VAL(4) |
706 FRAC_PLL_OUTPUT_DIV_VAL(divq);
707 break;
708 default:
709 return -EINVAL;
710 }
711
712 /* bypass the clock */
713 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
714 /* Set the value */
715 writel(val_cfg1, pll_cfg1);
716 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
717 val_cfg0 = readl(pll_cfg0);
718 /* unbypass the clock */
719 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
720 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
721 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
722 if (ret)
723 printf("%s timeout\n", __func__);
724 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
725
726 return 0;
727 }
728
729
clock_init(void)730 int clock_init(void)
731 {
732 u32 grade;
733
734 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
735 CLK_ROOT_SOURCE_SEL(0));
736
737 /*
738 * 8MQ only supports two grades: consumer and industrial.
739 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
740 */
741 grade = get_cpu_temp_grade(NULL, NULL);
742 if (!grade)
743 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
744 else
745 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
746
747 /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
748 clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
749
750 /*
751 * According to ANAMIX SPEC
752 * sys pll1 fixed at 800MHz
753 * sys pll2 fixed at 1GHz
754 * Here we only enable the outputs.
755 */
756 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
757 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
758 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
759 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
760 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
761
762 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
763 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
764 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
765 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
766 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
767
768 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
769 CLK_ROOT_SOURCE_SEL(1));
770
771 init_wdog_clk();
772 clock_enable(CCGR_TSENSOR, 1);
773 clock_enable(CCGR_OCOTP, 1);
774
775 /* config GIC ROOT to sys_pll2_200m */
776 clock_enable(CCGR_GIC, 0);
777 clock_set_target_val(GIC_CLK_ROOT,
778 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
779 clock_enable(CCGR_GIC, 1);
780
781 return 0;
782 }
783 #endif
784
785 /*
786 * Dump some clockes.
787 */
788 #ifndef CONFIG_SPL_BUILD
do_imx8m_showclocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])789 static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
790 char *const argv[])
791 {
792 u32 freq;
793
794 freq = decode_frac_pll(ARM_PLL_CLK);
795 printf("ARM_PLL %8d MHz\n", freq / 1000000);
796 freq = decode_sscg_pll(DRAM_PLL1_CLK);
797 printf("DRAM_PLL %8d MHz\n", freq / 1000000);
798 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
799 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
800 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
801 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
802 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
803 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
804 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
805 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
806 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
807 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
808 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
809 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
810 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
811 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
812 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
813 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
814 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
815 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
816 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
817 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
818 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
819 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
820 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
821 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
822 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
823 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
824 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
825 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
826 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
827 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
828 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
829 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
830 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
831 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
832 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
833 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
834 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
835 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
836 freq = mxc_get_clock(UART1_CLK_ROOT);
837 printf("UART1 %8d MHz\n", freq / 1000000);
838 freq = mxc_get_clock(USDHC1_CLK_ROOT);
839 printf("USDHC1 %8d MHz\n", freq / 1000000);
840 freq = mxc_get_clock(QSPI_CLK_ROOT);
841 printf("QSPI %8d MHz\n", freq / 1000000);
842 return 0;
843 }
844
845 U_BOOT_CMD(
846 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
847 "display clocks",
848 ""
849 );
850 #endif
851