1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/hab.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/syscounter.h>
20 #include <asm/ptrace.h>
21 #include <asm/armv8/mmu.h>
22 #include <dm/uclass.h>
23 #include <efi_loader.h>
24 #include <env.h>
25 #include <env_internal.h>
26 #include <errno.h>
27 #include <fdt_support.h>
28 #include <fsl_wdog.h>
29 #include <imx_sip.h>
30 #include <linux/arm-smccc.h>
31 #include <linux/bitops.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #if defined(CONFIG_IMX_HAB)
36 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
37 .bank = 1,
38 .word = 3,
39 };
40 #endif
41
timer_init(void)42 int timer_init(void)
43 {
44 #ifdef CONFIG_SPL_BUILD
45 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
46 unsigned long freq = readl(&sctr->cntfid0);
47
48 /* Update with accurate clock frequency */
49 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
50
51 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
52 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
53 #endif
54
55 gd->arch.tbl = 0;
56 gd->arch.tbu = 0;
57
58 return 0;
59 }
60
enable_tzc380(void)61 void enable_tzc380(void)
62 {
63 struct iomuxc_gpr_base_regs *gpr =
64 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
65
66 /* Enable TZASC and lock setting */
67 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
68 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
69 if (is_imx8mm() || is_imx8mn() || is_imx8mp())
70 setbits_le32(&gpr->gpr[10], BIT(1));
71 /*
72 * set Region 0 attribute to allow secure and non-secure
73 * read/write permission. Found some masters like usb dwc3
74 * controllers can't work with secure memory.
75 */
76 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
77 }
78
set_wdog_reset(struct wdog_regs * wdog)79 void set_wdog_reset(struct wdog_regs *wdog)
80 {
81 /*
82 * Output WDOG_B signal to reset external pmic or POR_B decided by
83 * the board design. Without external reset, the peripherals/DDR/
84 * PMIC are not reset, that may cause system working abnormal.
85 * WDZST bit is write-once only bit. Align this bit in kernel,
86 * otherwise kernel code will have no chance to set this bit.
87 */
88 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
89 }
90
91 static struct mm_region imx8m_mem_map[] = {
92 {
93 /* ROM */
94 .virt = 0x0UL,
95 .phys = 0x0UL,
96 .size = 0x100000UL,
97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_OUTER_SHARE
99 }, {
100 /* CAAM */
101 .virt = 0x100000UL,
102 .phys = 0x100000UL,
103 .size = 0x8000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN
107 }, {
108 /* OCRAM_S */
109 .virt = 0x180000UL,
110 .phys = 0x180000UL,
111 .size = 0x8000UL,
112 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
113 PTE_BLOCK_OUTER_SHARE
114 }, {
115 /* TCM */
116 .virt = 0x7C0000UL,
117 .phys = 0x7C0000UL,
118 .size = 0x80000UL,
119 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
120 PTE_BLOCK_NON_SHARE |
121 PTE_BLOCK_PXN | PTE_BLOCK_UXN
122 }, {
123 /* OCRAM */
124 .virt = 0x900000UL,
125 .phys = 0x900000UL,
126 .size = 0x200000UL,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
128 PTE_BLOCK_OUTER_SHARE
129 }, {
130 /* AIPS */
131 .virt = 0xB00000UL,
132 .phys = 0xB00000UL,
133 .size = 0x3f500000UL,
134 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
135 PTE_BLOCK_NON_SHARE |
136 PTE_BLOCK_PXN | PTE_BLOCK_UXN
137 }, {
138 /* DRAM1 */
139 .virt = 0x40000000UL,
140 .phys = 0x40000000UL,
141 .size = PHYS_SDRAM_SIZE,
142 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
143 PTE_BLOCK_OUTER_SHARE
144 #ifdef PHYS_SDRAM_2_SIZE
145 }, {
146 /* DRAM2 */
147 .virt = 0x100000000UL,
148 .phys = 0x100000000UL,
149 .size = PHYS_SDRAM_2_SIZE,
150 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
151 PTE_BLOCK_OUTER_SHARE
152 #endif
153 }, {
154 /* empty entrie to split table entry 5 if needed when TEEs are used */
155 0,
156 }, {
157 /* List terminator */
158 0,
159 }
160 };
161
162 struct mm_region *mem_map = imx8m_mem_map;
163
imx8m_find_dram_entry_in_mem_map(void)164 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
165 {
166 int i;
167
168 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
169 if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
170 return i;
171
172 hang(); /* Entry not found, this must never happen. */
173 }
174
enable_caches(void)175 void enable_caches(void)
176 {
177 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
178 if (rom_pointer[1]) {
179 /*
180 * TEE are loaded, So the ddr bank structures
181 * have been modified update mmu table accordingly
182 */
183 int i = 0;
184 /*
185 * please make sure that entry initial value matches
186 * imx8m_mem_map for DRAM1
187 */
188 int entry = imx8m_find_dram_entry_in_mem_map();
189 u64 attrs = imx8m_mem_map[entry].attrs;
190
191 while (i < CONFIG_NR_DRAM_BANKS &&
192 entry < ARRAY_SIZE(imx8m_mem_map)) {
193 if (gd->bd->bi_dram[i].start == 0)
194 break;
195 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
196 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
197 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
198 imx8m_mem_map[entry].attrs = attrs;
199 debug("Added memory mapping (%d): %llx %llx\n", entry,
200 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
201 i++; entry++;
202 }
203 }
204
205 icache_enable();
206 dcache_enable();
207 }
208
board_phys_sdram_size(phys_size_t * size)209 __weak int board_phys_sdram_size(phys_size_t *size)
210 {
211 if (!size)
212 return -EINVAL;
213
214 *size = PHYS_SDRAM_SIZE;
215 return 0;
216 }
217
dram_init(void)218 int dram_init(void)
219 {
220 unsigned int entry = imx8m_find_dram_entry_in_mem_map();
221 phys_size_t sdram_size;
222 int ret;
223
224 ret = board_phys_sdram_size(&sdram_size);
225 if (ret)
226 return ret;
227
228 /* rom_pointer[1] contains the size of TEE occupies */
229 if (rom_pointer[1])
230 gd->ram_size = sdram_size - rom_pointer[1];
231 else
232 gd->ram_size = sdram_size;
233
234 /* also update the SDRAM size in the mem_map used externally */
235 imx8m_mem_map[entry].size = sdram_size;
236
237 #ifdef PHYS_SDRAM_2_SIZE
238 gd->ram_size += PHYS_SDRAM_2_SIZE;
239 #endif
240
241 return 0;
242 }
243
dram_init_banksize(void)244 int dram_init_banksize(void)
245 {
246 int bank = 0;
247 int ret;
248 phys_size_t sdram_size;
249
250 ret = board_phys_sdram_size(&sdram_size);
251 if (ret)
252 return ret;
253
254 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
255 if (rom_pointer[1]) {
256 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
257 phys_size_t optee_size = (size_t)rom_pointer[1];
258
259 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
260 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
261 if (++bank >= CONFIG_NR_DRAM_BANKS) {
262 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
263 return -1;
264 }
265
266 gd->bd->bi_dram[bank].start = optee_start + optee_size;
267 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
268 sdram_size - gd->bd->bi_dram[bank].start;
269 }
270 } else {
271 gd->bd->bi_dram[bank].size = sdram_size;
272 }
273
274 #ifdef PHYS_SDRAM_2_SIZE
275 if (++bank >= CONFIG_NR_DRAM_BANKS) {
276 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
277 return -1;
278 }
279 gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
280 gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
281 #endif
282
283 return 0;
284 }
285
get_effective_memsize(void)286 phys_size_t get_effective_memsize(void)
287 {
288 /* return the first bank as effective memory */
289 if (rom_pointer[1])
290 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
291
292 #ifdef PHYS_SDRAM_2_SIZE
293 return gd->ram_size - PHYS_SDRAM_2_SIZE;
294 #else
295 return gd->ram_size;
296 #endif
297 }
298
board_get_usable_ram_top(ulong total_size)299 ulong board_get_usable_ram_top(ulong total_size)
300 {
301 ulong top_addr = PHYS_SDRAM + gd->ram_size;
302
303 /*
304 * Some IPs have their accessible address space restricted by
305 * the interconnect. Let's make sure U-Boot only ever uses the
306 * space below the 4G address boundary (which is 3GiB big),
307 * even when the effective available memory is bigger.
308 */
309 if (top_addr > 0x80000000)
310 top_addr = 0x80000000;
311
312 /*
313 * rom_pointer[0] stores the TEE memory start address.
314 * rom_pointer[1] stores the size TEE uses.
315 * We need to reserve the memory region for TEE.
316 */
317 if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
318 top_addr = rom_pointer[0];
319
320 return top_addr;
321 }
322
get_cpu_variant_type(u32 type)323 static u32 get_cpu_variant_type(u32 type)
324 {
325 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
326 struct fuse_bank *bank = &ocotp->bank[1];
327 struct fuse_bank1_regs *fuse =
328 (struct fuse_bank1_regs *)bank->fuse_regs;
329
330 u32 value = readl(&fuse->tester4);
331
332 if (type == MXC_CPU_IMX8MQ) {
333 if ((value & 0x3) == 0x2)
334 return MXC_CPU_IMX8MD;
335 else if (value & 0x200000)
336 return MXC_CPU_IMX8MQL;
337
338 } else if (type == MXC_CPU_IMX8MM) {
339 switch (value & 0x3) {
340 case 2:
341 if (value & 0x1c0000)
342 return MXC_CPU_IMX8MMDL;
343 else
344 return MXC_CPU_IMX8MMD;
345 case 3:
346 if (value & 0x1c0000)
347 return MXC_CPU_IMX8MMSL;
348 else
349 return MXC_CPU_IMX8MMS;
350 default:
351 if (value & 0x1c0000)
352 return MXC_CPU_IMX8MML;
353 break;
354 }
355 } else if (type == MXC_CPU_IMX8MN) {
356 switch (value & 0x3) {
357 case 2:
358 if (value & 0x1000000) {
359 if (value & 0x10000000) /* MIPI DSI */
360 return MXC_CPU_IMX8MNUD;
361 else
362 return MXC_CPU_IMX8MNDL;
363 } else {
364 return MXC_CPU_IMX8MND;
365 }
366 case 3:
367 if (value & 0x1000000) {
368 if (value & 0x10000000) /* MIPI DSI */
369 return MXC_CPU_IMX8MNUS;
370 else
371 return MXC_CPU_IMX8MNSL;
372 } else {
373 return MXC_CPU_IMX8MNS;
374 }
375 default:
376 if (value & 0x1000000) {
377 if (value & 0x10000000) /* MIPI DSI */
378 return MXC_CPU_IMX8MNUQ;
379 else
380 return MXC_CPU_IMX8MNL;
381 }
382 break;
383 }
384 } else if (type == MXC_CPU_IMX8MP) {
385 u32 value0 = readl(&fuse->tester3);
386 u32 flag = 0;
387
388 if ((value0 & 0xc0000) == 0x80000)
389 return MXC_CPU_IMX8MPD;
390
391 /* vpu disabled */
392 if ((value0 & 0x43000000) == 0x43000000)
393 flag = 1;
394
395 /* npu disabled*/
396 if ((value & 0x8) == 0x8)
397 flag |= (1 << 1);
398
399 /* isp disabled */
400 if ((value & 0x3) == 0x3)
401 flag |= (1 << 2);
402
403 switch (flag) {
404 case 7:
405 return MXC_CPU_IMX8MPL;
406 case 2:
407 return MXC_CPU_IMX8MP6;
408 default:
409 break;
410 }
411
412 }
413
414 return type;
415 }
416
get_cpu_rev(void)417 u32 get_cpu_rev(void)
418 {
419 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
420 u32 reg = readl(&ana_pll->digprog);
421 u32 type = (reg >> 16) & 0xff;
422 u32 major_low = (reg >> 8) & 0xff;
423 u32 rom_version;
424
425 reg &= 0xff;
426
427 /* iMX8MP */
428 if (major_low == 0x43) {
429 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
430 } else if (major_low == 0x42) {
431 /* iMX8MN */
432 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
433 } else if (major_low == 0x41) {
434 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
435 } else {
436 if (reg == CHIP_REV_1_0) {
437 /*
438 * For B0 chip, the DIGPROG is not updated,
439 * it is still TO1.0. we have to check ROM
440 * version or OCOTP_READ_FUSE_DATA.
441 * 0xff0055aa is magic number for B1.
442 */
443 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
444 /*
445 * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
446 * so have to check ROM to distinguish them
447 */
448 rom_version = readl((void __iomem *)ROM_VERSION_B0);
449 rom_version &= 0xff;
450 if (rom_version == CHIP_REV_2_2)
451 reg = CHIP_REV_2_2;
452 else
453 reg = CHIP_REV_2_1;
454 } else {
455 rom_version =
456 readl((void __iomem *)ROM_VERSION_A0);
457 if (rom_version != CHIP_REV_1_0) {
458 rom_version = readl((void __iomem *)ROM_VERSION_B0);
459 rom_version &= 0xff;
460 if (rom_version == CHIP_REV_2_0)
461 reg = CHIP_REV_2_0;
462 }
463 }
464 }
465
466 type = get_cpu_variant_type(type);
467 }
468
469 return (type << 12) | reg;
470 }
471
imx_set_wdog_powerdown(bool enable)472 static void imx_set_wdog_powerdown(bool enable)
473 {
474 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
475 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
476 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
477
478 /* Write to the PDE (Power Down Enable) bit */
479 writew(enable, &wdog1->wmcr);
480 writew(enable, &wdog2->wmcr);
481 writew(enable, &wdog3->wmcr);
482 }
483
arch_cpu_init_dm(void)484 int arch_cpu_init_dm(void)
485 {
486 struct udevice *dev;
487 int ret;
488
489 if (CONFIG_IS_ENABLED(CLK)) {
490 ret = uclass_get_device_by_name(UCLASS_CLK,
491 "clock-controller@30380000",
492 &dev);
493 if (ret < 0) {
494 printf("Failed to find clock node. Check device tree\n");
495 return ret;
496 }
497 }
498
499 return 0;
500 }
501
arch_cpu_init(void)502 int arch_cpu_init(void)
503 {
504 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
505 /*
506 * ROM might disable clock for SCTR,
507 * enable the clock before timer_init.
508 */
509 if (IS_ENABLED(CONFIG_SPL_BUILD))
510 clock_enable(CCGR_SCTR, 1);
511 /*
512 * Init timer at very early state, because sscg pll setting
513 * will use it
514 */
515 timer_init();
516
517 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
518 clock_init();
519 imx_set_wdog_powerdown(false);
520
521 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
522 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
523 is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
524 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
525 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
526 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
527 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
528 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
529
530 writel(0x1, &pgc_core2->pgcr);
531 writel(0x1, &pgc_core3->pgcr);
532 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
533 writel(0x1, &pgc_core1->pgcr);
534 writel(0xE, &gpc->cpu_pgc_dn_trg);
535 } else {
536 writel(0xC, &gpc->cpu_pgc_dn_trg);
537 }
538 }
539 }
540
541 if (is_imx8mq()) {
542 clock_enable(CCGR_OCOTP, 1);
543 if (readl(&ocotp->ctrl) & 0x200)
544 writel(0x200, &ocotp->ctrl_clr);
545 }
546
547 return 0;
548 }
549
550 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
551 struct rom_api *g_rom_api = (struct rom_api *)0x980;
552
get_boot_device(void)553 enum boot_device get_boot_device(void)
554 {
555 volatile gd_t *pgd = gd;
556 int ret;
557 u32 boot;
558 u16 boot_type;
559 u8 boot_instance;
560 enum boot_device boot_dev = SD1_BOOT;
561
562 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
563 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
564 set_gd(pgd);
565
566 if (ret != ROM_API_OKAY) {
567 puts("ROMAPI: failure at query_boot_info\n");
568 return -1;
569 }
570
571 boot_type = boot >> 16;
572 boot_instance = (boot >> 8) & 0xff;
573
574 switch (boot_type) {
575 case BT_DEV_TYPE_SD:
576 boot_dev = boot_instance + SD1_BOOT;
577 break;
578 case BT_DEV_TYPE_MMC:
579 boot_dev = boot_instance + MMC1_BOOT;
580 break;
581 case BT_DEV_TYPE_NAND:
582 boot_dev = NAND_BOOT;
583 break;
584 case BT_DEV_TYPE_FLEXSPINOR:
585 boot_dev = QSPI_BOOT;
586 break;
587 case BT_DEV_TYPE_USB:
588 boot_dev = USB_BOOT;
589 break;
590 default:
591 break;
592 }
593
594 return boot_dev;
595 }
596 #endif
597
598 #if defined(CONFIG_IMX8M)
599 #include <spl.h>
spl_mmc_emmc_boot_partition(struct mmc * mmc)600 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
601 {
602 u32 *rom_log_addr = (u32 *)0x9e0;
603 u32 *rom_log;
604 u8 event_id;
605 int i, part;
606
607 part = default_spl_mmc_emmc_boot_partition(mmc);
608
609 /* If the ROM event log pointer is not valid. */
610 if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
611 *rom_log_addr & 0x3)
612 return part;
613
614 /* Parse the ROM event ID version 2 log */
615 rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
616 for (i = 0; i < 128; i++) {
617 event_id = rom_log[i] >> 24;
618 switch (event_id) {
619 case 0x00: /* End of list */
620 return part;
621 /* Log entries with 1 parameter, skip 1 */
622 case 0x80: /* Start to perform the device initialization */
623 case 0x81: /* The boot device initialization completes */
624 case 0x8f: /* The boot device initialization fails */
625 case 0x90: /* Start to read data from boot device */
626 case 0x91: /* Reading data from boot device completes */
627 case 0x9f: /* Reading data from boot device fails */
628 i += 1;
629 continue;
630 /* Log entries with 2 parameters, skip 2 */
631 case 0xa0: /* Image authentication result */
632 case 0xc0: /* Jump to the boot image soon */
633 i += 2;
634 continue;
635 /* Boot from the secondary boot image */
636 case 0x51:
637 /*
638 * Swap the eMMC boot partitions in case there was a
639 * fallback event (i.e. primary image was corrupted
640 * and that corruption was recognized by the BootROM),
641 * so the SPL loads the rest of the U-Boot from the
642 * correct eMMC boot partition, since the BootROM
643 * leaves the boot partition set to the corrupted one.
644 */
645 if (part == 1)
646 part = 2;
647 else if (part == 2)
648 part = 1;
649 continue;
650 default:
651 continue;
652 }
653 }
654
655 return part;
656 }
657 #endif
658
is_usb_boot(void)659 bool is_usb_boot(void)
660 {
661 return get_boot_device() == USB_BOOT;
662 }
663
664 #ifdef CONFIG_OF_SYSTEM_SETUP
check_fdt_new_path(void * blob)665 bool check_fdt_new_path(void *blob)
666 {
667 const char *soc_path = "/soc@0";
668 int nodeoff;
669
670 nodeoff = fdt_path_offset(blob, soc_path);
671 if (nodeoff < 0)
672 return false;
673
674 return true;
675 }
676
disable_fdt_nodes(void * blob,const char * const nodes_path[],int size_array)677 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
678 {
679 int i = 0;
680 int rc;
681 int nodeoff;
682 const char *status = "disabled";
683
684 for (i = 0; i < size_array; i++) {
685 nodeoff = fdt_path_offset(blob, nodes_path[i]);
686 if (nodeoff < 0)
687 continue; /* Not found, skip it */
688
689 printf("Found %s node\n", nodes_path[i]);
690
691 add_status:
692 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
693 if (rc) {
694 if (rc == -FDT_ERR_NOSPACE) {
695 rc = fdt_increase_size(blob, 512);
696 if (!rc)
697 goto add_status;
698 }
699 printf("Unable to update property %s:%s, err=%s\n",
700 nodes_path[i], "status", fdt_strerror(rc));
701 } else {
702 printf("Modify %s:%s disabled\n",
703 nodes_path[i], "status");
704 }
705 }
706
707 return 0;
708 }
709
710 #ifdef CONFIG_IMX8MQ
check_dcss_fused(void)711 bool check_dcss_fused(void)
712 {
713 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
714 struct fuse_bank *bank = &ocotp->bank[1];
715 struct fuse_bank1_regs *fuse =
716 (struct fuse_bank1_regs *)bank->fuse_regs;
717 u32 value = readl(&fuse->tester4);
718
719 if (value & 0x4000000)
720 return true;
721
722 return false;
723 }
724
disable_mipi_dsi_nodes(void * blob)725 static int disable_mipi_dsi_nodes(void *blob)
726 {
727 static const char * const nodes_path[] = {
728 "/mipi_dsi@30A00000",
729 "/mipi_dsi_bridge@30A00000",
730 "/dsi_phy@30A00300",
731 "/soc@0/bus@30800000/mipi_dsi@30a00000",
732 "/soc@0/bus@30800000/dphy@30a00300",
733 "/soc@0/bus@30800000/mipi-dsi@30a00000",
734 };
735
736 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
737 }
738
disable_dcss_nodes(void * blob)739 static int disable_dcss_nodes(void *blob)
740 {
741 static const char * const nodes_path[] = {
742 "/dcss@0x32e00000",
743 "/dcss@32e00000",
744 "/hdmi@32c00000",
745 "/hdmi_cec@32c33800",
746 "/hdmi_drm@32c00000",
747 "/display-subsystem",
748 "/sound-hdmi",
749 "/sound-hdmi-arc",
750 "/soc@0/bus@32c00000/display-controller@32e00000",
751 "/soc@0/bus@32c00000/hdmi@32c00000",
752 };
753
754 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
755 }
756
check_mipi_dsi_nodes(void * blob)757 static int check_mipi_dsi_nodes(void *blob)
758 {
759 static const char * const lcdif_path[] = {
760 "/lcdif@30320000",
761 "/soc@0/bus@30000000/lcdif@30320000",
762 "/soc@0/bus@30000000/lcd-controller@30320000"
763 };
764 static const char * const mipi_dsi_path[] = {
765 "/mipi_dsi@30A00000",
766 "/soc@0/bus@30800000/mipi_dsi@30a00000"
767 };
768 static const char * const lcdif_ep_path[] = {
769 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
770 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
771 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
772 };
773 static const char * const mipi_dsi_ep_path[] = {
774 "/mipi_dsi@30A00000/port@1/endpoint",
775 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
776 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
777 };
778
779 int lookup_node;
780 int nodeoff;
781 bool new_path = check_fdt_new_path(blob);
782 int i = new_path ? 1 : 0;
783
784 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
785 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
786 /*
787 * If can't find lcdif node or lcdif node is disabled,
788 * then disable all mipi dsi, since they only can input
789 * from DCSS
790 */
791 return disable_mipi_dsi_nodes(blob);
792 }
793
794 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
795 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
796 return 0;
797
798 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
799 if (nodeoff < 0) {
800 /*
801 * If can't find lcdif endpoint, then disable all mipi dsi,
802 * since they only can input from DCSS
803 */
804 return disable_mipi_dsi_nodes(blob);
805 }
806
807 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
808 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
809
810 if (nodeoff > 0 && nodeoff == lookup_node)
811 return 0;
812
813 return disable_mipi_dsi_nodes(blob);
814 }
815 #endif
816
disable_vpu_nodes(void * blob)817 int disable_vpu_nodes(void *blob)
818 {
819 static const char * const nodes_path_8mq[] = {
820 "/vpu@38300000",
821 "/soc@0/vpu@38300000"
822 };
823
824 static const char * const nodes_path_8mm[] = {
825 "/vpu_g1@38300000",
826 "/vpu_g2@38310000",
827 "/vpu_h1@38320000"
828 };
829
830 static const char * const nodes_path_8mp[] = {
831 "/vpu_g1@38300000",
832 "/vpu_g2@38310000",
833 "/vpu_vc8000e@38320000"
834 };
835
836 if (is_imx8mq())
837 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
838 else if (is_imx8mm())
839 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
840 else if (is_imx8mp())
841 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
842 else
843 return -EPERM;
844 }
845
846 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
low_drive_gpu_freq(void * blob)847 static int low_drive_gpu_freq(void *blob)
848 {
849 static const char *nodes_path_8mn[] = {
850 "/gpu@38000000",
851 "/soc@0/gpu@38000000"
852 };
853
854 int nodeoff, cnt, i;
855 u32 assignedclks[7];
856
857 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
858 if (nodeoff < 0)
859 return nodeoff;
860
861 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
862 if (cnt < 0)
863 return cnt;
864
865 if (cnt != 7)
866 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
867
868 assignedclks[cnt - 1] = 200000000;
869 assignedclks[cnt - 2] = 200000000;
870
871 for (i = 0; i < cnt; i++) {
872 debug("<%u>, ", assignedclks[i]);
873 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
874 }
875 debug("\n");
876
877 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
878 }
879 #endif
880
disable_gpu_nodes(void * blob)881 int disable_gpu_nodes(void *blob)
882 {
883 static const char * const nodes_path_8mn[] = {
884 "/gpu@38000000",
885 "/soc@/gpu@38000000"
886 };
887
888 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
889 }
890
disable_npu_nodes(void * blob)891 int disable_npu_nodes(void *blob)
892 {
893 static const char * const nodes_path_8mp[] = {
894 "/vipsi@38500000"
895 };
896
897 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
898 }
899
disable_isp_nodes(void * blob)900 int disable_isp_nodes(void *blob)
901 {
902 static const char * const nodes_path_8mp[] = {
903 "/soc@0/bus@32c00000/camera/isp@32e10000",
904 "/soc@0/bus@32c00000/camera/isp@32e20000"
905 };
906
907 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
908 }
909
disable_dsp_nodes(void * blob)910 int disable_dsp_nodes(void *blob)
911 {
912 static const char * const nodes_path_8mp[] = {
913 "/dsp@3b6e8000"
914 };
915
916 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
917 }
918
disable_thermal_cpu_nodes(void * blob,u32 disabled_cores)919 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
920 {
921 static const char * const thermal_path[] = {
922 "/thermal-zones/cpu-thermal/cooling-maps/map0"
923 };
924
925 int nodeoff, cnt, i, ret, j;
926 u32 cooling_dev[12];
927
928 for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
929 nodeoff = fdt_path_offset(blob, thermal_path[i]);
930 if (nodeoff < 0)
931 continue; /* Not found, skip it */
932
933 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
934 if (cnt < 0)
935 continue;
936
937 if (cnt != 12)
938 printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
939
940 for (j = 0; j < cnt; j++)
941 cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
942
943 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
944 sizeof(u32) * (12 - disabled_cores * 3));
945 if (ret < 0) {
946 printf("Warning: %s, cooling-device setprop failed %d\n",
947 thermal_path[i], ret);
948 continue;
949 }
950
951 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
952 }
953 }
954
disable_pmu_cpu_nodes(void * blob,u32 disabled_cores)955 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
956 {
957 static const char * const pmu_path[] = {
958 "/pmu"
959 };
960
961 int nodeoff, cnt, i, ret, j;
962 u32 irq_affinity[4];
963
964 for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
965 nodeoff = fdt_path_offset(blob, pmu_path[i]);
966 if (nodeoff < 0)
967 continue; /* Not found, skip it */
968
969 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
970 irq_affinity, 4);
971 if (cnt < 0)
972 continue;
973
974 if (cnt != 4)
975 printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
976
977 for (j = 0; j < cnt; j++)
978 irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
979
980 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
981 sizeof(u32) * (4 - disabled_cores));
982 if (ret < 0) {
983 printf("Warning: %s, interrupt-affinity setprop failed %d\n",
984 pmu_path[i], ret);
985 continue;
986 }
987
988 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
989 }
990 }
991
disable_cpu_nodes(void * blob,u32 disabled_cores)992 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
993 {
994 static const char * const nodes_path[] = {
995 "/cpus/cpu@1",
996 "/cpus/cpu@2",
997 "/cpus/cpu@3",
998 };
999 u32 i = 0;
1000 int rc;
1001 int nodeoff;
1002
1003 if (disabled_cores > 3)
1004 return -EINVAL;
1005
1006 i = 3 - disabled_cores;
1007
1008 for (; i < 3; i++) {
1009 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1010 if (nodeoff < 0)
1011 continue; /* Not found, skip it */
1012
1013 debug("Found %s node\n", nodes_path[i]);
1014
1015 rc = fdt_del_node(blob, nodeoff);
1016 if (rc < 0) {
1017 printf("Unable to delete node %s, err=%s\n",
1018 nodes_path[i], fdt_strerror(rc));
1019 } else {
1020 printf("Delete node %s\n", nodes_path[i]);
1021 }
1022 }
1023
1024 disable_thermal_cpu_nodes(blob, disabled_cores);
1025 disable_pmu_cpu_nodes(blob, disabled_cores);
1026
1027 return 0;
1028 }
1029
ft_system_setup(void * blob,struct bd_info * bd)1030 int ft_system_setup(void *blob, struct bd_info *bd)
1031 {
1032 #ifdef CONFIG_IMX8MQ
1033 int i = 0;
1034 int rc;
1035 int nodeoff;
1036
1037 if (get_boot_device() == USB_BOOT) {
1038 disable_dcss_nodes(blob);
1039
1040 bool new_path = check_fdt_new_path(blob);
1041 int v = new_path ? 1 : 0;
1042 static const char * const usb_dwc3_path[] = {
1043 "/usb@38100000/dwc3",
1044 "/soc@0/usb@38100000"
1045 };
1046
1047 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1048 if (nodeoff >= 0) {
1049 const char *speed = "high-speed";
1050
1051 printf("Found %s node\n", usb_dwc3_path[v]);
1052
1053 usb_modify_speed:
1054
1055 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1056 if (rc) {
1057 if (rc == -FDT_ERR_NOSPACE) {
1058 rc = fdt_increase_size(blob, 512);
1059 if (!rc)
1060 goto usb_modify_speed;
1061 }
1062 printf("Unable to set property %s:%s, err=%s\n",
1063 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1064 } else {
1065 printf("Modify %s:%s = %s\n",
1066 usb_dwc3_path[v], "maximum-speed", speed);
1067 }
1068 } else {
1069 printf("Can't found %s node\n", usb_dwc3_path[v]);
1070 }
1071 }
1072
1073 /* Disable the CPU idle for A0 chip since the HW does not support it */
1074 if (is_soc_rev(CHIP_REV_1_0)) {
1075 static const char * const nodes_path[] = {
1076 "/cpus/cpu@0",
1077 "/cpus/cpu@1",
1078 "/cpus/cpu@2",
1079 "/cpus/cpu@3",
1080 };
1081
1082 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1083 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1084 if (nodeoff < 0)
1085 continue; /* Not found, skip it */
1086
1087 debug("Found %s node\n", nodes_path[i]);
1088
1089 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1090 if (rc == -FDT_ERR_NOTFOUND)
1091 continue;
1092 if (rc) {
1093 printf("Unable to update property %s:%s, err=%s\n",
1094 nodes_path[i], "status", fdt_strerror(rc));
1095 return rc;
1096 }
1097
1098 debug("Remove %s:%s\n", nodes_path[i],
1099 "cpu-idle-states");
1100 }
1101 }
1102
1103 if (is_imx8mql()) {
1104 disable_vpu_nodes(blob);
1105 if (check_dcss_fused()) {
1106 printf("DCSS is fused\n");
1107 disable_dcss_nodes(blob);
1108 check_mipi_dsi_nodes(blob);
1109 }
1110 }
1111
1112 if (is_imx8md())
1113 disable_cpu_nodes(blob, 2);
1114
1115 #elif defined(CONFIG_IMX8MM)
1116 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
1117 disable_vpu_nodes(blob);
1118
1119 if (is_imx8mmd() || is_imx8mmdl())
1120 disable_cpu_nodes(blob, 2);
1121 else if (is_imx8mms() || is_imx8mmsl())
1122 disable_cpu_nodes(blob, 3);
1123
1124 #elif defined(CONFIG_IMX8MN)
1125 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1126 disable_gpu_nodes(blob);
1127 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1128 else {
1129 int ldm_gpu = low_drive_gpu_freq(blob);
1130
1131 if (ldm_gpu < 0)
1132 printf("Update GPU node assigned-clock-rates failed\n");
1133 else
1134 printf("Update GPU node assigned-clock-rates ok\n");
1135 }
1136 #endif
1137
1138 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1139 disable_cpu_nodes(blob, 2);
1140 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1141 disable_cpu_nodes(blob, 3);
1142
1143 #elif defined(CONFIG_IMX8MP)
1144 if (is_imx8mpl())
1145 disable_vpu_nodes(blob);
1146
1147 if (is_imx8mpl() || is_imx8mp6())
1148 disable_npu_nodes(blob);
1149
1150 if (is_imx8mpl())
1151 disable_isp_nodes(blob);
1152
1153 if (is_imx8mpl() || is_imx8mp6())
1154 disable_dsp_nodes(blob);
1155
1156 if (is_imx8mpd())
1157 disable_cpu_nodes(blob, 2);
1158 #endif
1159
1160 return 0;
1161 }
1162 #endif
1163
1164 #if !CONFIG_IS_ENABLED(SYSRESET)
reset_cpu(void)1165 void reset_cpu(void)
1166 {
1167 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1168
1169 /* Clear WDA to trigger WDOG_B immediately */
1170 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1171
1172 while (1) {
1173 /*
1174 * spin for .5 seconds before reset
1175 */
1176 }
1177 }
1178 #endif
1179
1180 #if defined(CONFIG_ARCH_MISC_INIT)
acquire_buildinfo(void)1181 static void acquire_buildinfo(void)
1182 {
1183 u64 atf_commit = 0;
1184 struct arm_smccc_res res;
1185
1186 /* Get ARM Trusted Firmware commit id */
1187 arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
1188 0, 0, 0, 0, 0, 0, &res);
1189 atf_commit = res.a0;
1190 if (atf_commit == 0xffffffff) {
1191 debug("ATF does not support build info\n");
1192 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
1193 }
1194
1195 printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
1196 }
1197
arch_misc_init(void)1198 int arch_misc_init(void)
1199 {
1200 acquire_buildinfo();
1201
1202 return 0;
1203 }
1204 #endif
1205
imx_tmu_arch_init(void * reg_base)1206 void imx_tmu_arch_init(void *reg_base)
1207 {
1208 if (is_imx8mm() || is_imx8mn()) {
1209 /* Load TCALIV and TASR from fuses */
1210 struct ocotp_regs *ocotp =
1211 (struct ocotp_regs *)OCOTP_BASE_ADDR;
1212 struct fuse_bank *bank = &ocotp->bank[3];
1213 struct fuse_bank3_regs *fuse =
1214 (struct fuse_bank3_regs *)bank->fuse_regs;
1215
1216 u32 tca_rt, tca_hr, tca_en;
1217 u32 buf_vref, buf_slope;
1218
1219 tca_rt = fuse->ana0 & 0xFF;
1220 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
1221 tca_en = (fuse->ana0 & 0x2000000) >> 25;
1222
1223 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
1224 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
1225
1226 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1227 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
1228 (ulong)reg_base + 0x30);
1229 }
1230 #ifdef CONFIG_IMX8MP
1231 /* Load TCALIV0/1/m40 and TRIM from fuses */
1232 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1233 struct fuse_bank *bank = &ocotp->bank[38];
1234 struct fuse_bank38_regs *fuse =
1235 (struct fuse_bank38_regs *)bank->fuse_regs;
1236 struct fuse_bank *bank2 = &ocotp->bank[39];
1237 struct fuse_bank39_regs *fuse2 =
1238 (struct fuse_bank39_regs *)bank2->fuse_regs;
1239 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
1240 u32 reg;
1241 u32 tca40[2], tca25[2], tca105[2];
1242
1243 /* For blank sample */
1244 if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
1245 !fuse->ana_trim4 && !fuse2->ana_trim5) {
1246 /* Use a default 25C binary codes */
1247 tca25[0] = 1596;
1248 tca25[1] = 1596;
1249 writel(tca25[0], (ulong)reg_base + 0x30);
1250 writel(tca25[1], (ulong)reg_base + 0x34);
1251 return;
1252 }
1253
1254 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
1255 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1256 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1257 bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1258 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1259 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1260
1261 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
1262 writel(reg, (ulong)reg_base + 0x3c);
1263
1264 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1265 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1266 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1267 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1268 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1269 tca25[1] = fuse2->ana_trim5 & 0xFFF;
1270 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1271
1272 /* use 25c for 1p calibration */
1273 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1274 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1275 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1276 #endif
1277 }
1278
1279 #if defined(CONFIG_SPL_BUILD)
1280 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1281 bool serror_need_skip = true;
1282
do_error(struct pt_regs * pt_regs,unsigned int esr)1283 void do_error(struct pt_regs *pt_regs, unsigned int esr)
1284 {
1285 /*
1286 * If stack is still in ROM reserved OCRAM not switch to SPL,
1287 * it is the ROM SError
1288 */
1289 ulong sp;
1290
1291 asm volatile("mov %0, sp" : "=r"(sp) : );
1292
1293 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1294 /* Check for ERR050342, imx8mq HDCP enabled parts */
1295 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1296 serror_need_skip = false;
1297 return; /* Do nothing skip the SError in ROM */
1298 }
1299
1300 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1301 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1302 serror_need_skip = false;
1303 return; /* Do nothing skip the SError in ROM */
1304 }
1305 }
1306
1307 efi_restore_gd();
1308 printf("\"Error\" handler, esr 0x%08x\n", esr);
1309 show_regs(pt_regs);
1310 panic("Resetting CPU ...\n");
1311 }
1312 #endif
1313 #endif
1314
1315 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
env_get_location(enum env_operation op,int prio)1316 enum env_location env_get_location(enum env_operation op, int prio)
1317 {
1318 enum boot_device dev = get_boot_device();
1319 enum env_location env_loc = ENVL_UNKNOWN;
1320
1321 if (prio)
1322 return env_loc;
1323
1324 switch (dev) {
1325 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1326 case QSPI_BOOT:
1327 env_loc = ENVL_SPI_FLASH;
1328 break;
1329 #endif
1330 #ifdef CONFIG_ENV_IS_IN_NAND
1331 case NAND_BOOT:
1332 env_loc = ENVL_NAND;
1333 break;
1334 #endif
1335 #ifdef CONFIG_ENV_IS_IN_MMC
1336 case SD1_BOOT:
1337 case SD2_BOOT:
1338 case SD3_BOOT:
1339 case MMC1_BOOT:
1340 case MMC2_BOOT:
1341 case MMC3_BOOT:
1342 env_loc = ENVL_MMC;
1343 break;
1344 #endif
1345 default:
1346 #if defined(CONFIG_ENV_IS_NOWHERE)
1347 env_loc = ENVL_NOWHERE;
1348 #endif
1349 break;
1350 }
1351
1352 return env_loc;
1353 }
1354
1355 #ifndef ENV_IS_EMBEDDED
env_get_offset(long long defautl_offset)1356 long long env_get_offset(long long defautl_offset)
1357 {
1358 enum boot_device dev = get_boot_device();
1359
1360 switch (dev) {
1361 case NAND_BOOT:
1362 return (60 << 20); /* 60MB offset for NAND */
1363 default:
1364 break;
1365 }
1366
1367 return defautl_offset;
1368 }
1369 #endif
1370 #endif
1371