1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2021 NXP
4 */
5
6 #include <common.h>
7 #include <div64.h>
8 #include <asm/io.h>
9 #include <errno.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/cgc.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/global_data.h>
14 #include <linux/delay.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL;
19 static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL;
20
cgc1_soscdiv_init(void)21 void cgc1_soscdiv_init(void)
22 {
23 /* Configure SOSC/FRO DIV1 ~ DIV3 */
24 clrbits_le32(&cgc1_regs->soscdiv, BIT(7));
25 clrbits_le32(&cgc1_regs->soscdiv, BIT(15));
26 clrbits_le32(&cgc1_regs->soscdiv, BIT(23));
27 clrbits_le32(&cgc1_regs->soscdiv, BIT(31));
28
29 clrbits_le32(&cgc1_regs->frodiv, BIT(7));
30 }
31
cgc1_pll2_init(void)32 void cgc1_pll2_init(void)
33 {
34 u32 reg;
35
36 if (readl(&cgc1_regs->pll2csr) & BIT(23))
37 clrbits_le32(&cgc1_regs->pll2csr, BIT(23));
38
39 /* Disable PLL2 */
40 clrbits_le32(&cgc1_regs->pll2csr, BIT(0));
41 mdelay(1);
42
43 /* wait valid bit false */
44 while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
45 ;
46
47 /* Select SOSC as source, freq = 31 * 24 =744mhz */
48 reg = 31 << 16;
49 writel(reg, &cgc1_regs->pll2cfg);
50
51 /* Enable PLL2 */
52 setbits_le32(&cgc1_regs->pll2csr, BIT(0));
53
54 /* Wait for PLL2 clock ready */
55 while (!(readl(&cgc1_regs->pll2csr) & BIT(24)))
56 ;
57 }
58
cgc1_set_a35_clk(u32 clk_src,u32 div_core)59 static void cgc1_set_a35_clk(u32 clk_src, u32 div_core)
60 {
61 u32 reg;
62
63 /* ulock */
64 if (readl(&cgc1_regs->ca35clk) & BIT(31))
65 clrbits_le32(&cgc1_regs->ca35clk, BIT(31));
66
67 reg = readl(&cgc1_regs->ca35clk);
68 reg &= ~GENMASK(29, 21);
69 reg |= ((clk_src & 0x3) << 28);
70 reg |= (((div_core - 1) & 0x3f) << 21);
71 writel(reg, &cgc1_regs->ca35clk);
72
73 while (!(readl(&cgc1_regs->ca35clk) & BIT(27)))
74 ;
75 }
76
cgc1_init_core_clk(void)77 void cgc1_init_core_clk(void)
78 {
79 u32 reg = readl(&cgc1_regs->ca35clk);
80
81 /* if already selected to PLL2, switch to FRO firstly */
82 if (((reg >> 28) & 0x3) == 0x1)
83 cgc1_set_a35_clk(0, 1);
84
85 /* Set pll2 to 750Mhz for 1V */
86 cgc1_pll2_init();
87
88 /* Set A35 clock to pll2 */
89 cgc1_set_a35_clk(1, 1);
90 }
91
cgc1_enet_stamp_sel(u32 clk_src)92 void cgc1_enet_stamp_sel(u32 clk_src)
93 {
94 writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
95 }
96
cgc1_pll3_init(void)97 void cgc1_pll3_init(void)
98 {
99 /* Gate off VCO */
100 setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
101
102 /* Disable PLL3 */
103 clrbits_le32(&cgc1_regs->pll3csr, BIT(0));
104
105 /* Gate off PFDxDIV */
106 setbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
107 setbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
108
109 /* Gate off PFDx */
110 setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
111 setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
112 setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
113 setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
114
115 /* Select SOSC as source */
116 clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
117
118 //setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
119 writel(22 << 16, &cgc1_regs->pll3cfg);
120
121 writel(578, &cgc1_regs->pll3num);
122 writel(1000, &cgc1_regs->pll3denom);
123
124 /* Enable PLL3 */
125 setbits_le32(&cgc1_regs->pll3csr, BIT(0));
126
127 /* Wait for PLL3 clock ready */
128 while (!(readl(&cgc1_regs->pll3csr) & BIT(24)))
129 ;
130 /* Gate on VCO */
131 clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
132
133 /*
134 * PFD0: 380MHz/396/396/328
135 */
136 clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
137 setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
138 clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
139 while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
140 ;
141
142 clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
143 setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
144 clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
145 while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
146 ;
147
148 clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
149 setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
150 clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
151 while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
152 ;
153
154 clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24);
155 setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24);
156 clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
157 while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
158 ;
159
160 clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
161 clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
162 clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
163 clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(31));
164
165 clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7));
166 clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
167 clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
168 clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
169 }
170
cgc2_pll4_init(void)171 void cgc2_pll4_init(void)
172 {
173 /* Disable PFD DIV and clear DIV */
174 writel(0x80808080, &cgc2_regs->pll4div_pfd0);
175 writel(0x80808080, &cgc2_regs->pll4div_pfd1);
176
177 /* Gate off and clear PFD */
178 writel(0x80808080, &cgc2_regs->pll4pfdcfg);
179
180 /* Disable PLL4 */
181 writel(0x0, &cgc2_regs->pll4csr);
182
183 /* Configure PLL4 to 528Mhz and clock source from SOSC */
184 writel(22 << 16, &cgc2_regs->pll4cfg);
185 writel(0x1, &cgc2_regs->pll4csr);
186
187 /* wait for PLL4 output valid */
188 while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
189 ;
190
191 /* Enable all 4 PFDs */
192 setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */
193 setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8);
194 setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
195 setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
196
197 clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
198
199 while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(30) | BIT(22) | BIT(14) | BIT(6)))
200 != (BIT(30) | BIT(22) | BIT(14) | BIT(6)))
201 ;
202
203 /* Enable PFD DIV */
204 clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
205 clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
206 }
207
cgc2_ddrclk_config(u32 src,u32 div)208 void cgc2_ddrclk_config(u32 src, u32 div)
209 {
210 writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
211 /* wait for DDRCLK switching done */
212 while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
213 ;
214 }
215
decode_pll(enum cgc1_clk pll)216 u32 decode_pll(enum cgc1_clk pll)
217 {
218 u32 reg, infreq, mult;
219 u32 num, denom;
220
221 infreq = 24000000U;
222 /*
223 * Alought there are four choices for the bypass src,
224 * we choose SOSC 24M which is the default set in ROM.
225 * TODO: check more the comments
226 */
227 switch (pll) {
228 case PLL2:
229 reg = readl(&cgc1_regs->pll2csr);
230 if (!(reg & BIT(24)))
231 return 0;
232
233 reg = readl(&cgc1_regs->pll2cfg);
234 mult = (reg >> 16) & 0x7F;
235 denom = readl(&cgc1_regs->pll2denom) & 0x3FFFFFFF;
236 num = readl(&cgc1_regs->pll2num) & 0x3FFFFFFF;
237
238 return (u64)infreq * mult + (u64)infreq * num / denom;
239 case PLL3:
240 reg = readl(&cgc1_regs->pll3csr);
241 if (!(reg & BIT(24)))
242 return 0;
243
244 reg = readl(&cgc1_regs->pll3cfg);
245 mult = (reg >> 16) & 0x7F;
246 denom = readl(&cgc1_regs->pll3denom) & 0x3FFFFFFF;
247 num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF;
248
249 return (u64)infreq * mult + (u64)infreq * num / denom;
250 default:
251 printf("Unsupported pll clocks %d\n", pll);
252 break;
253 }
254
255 return 0;
256 }
257
cgc1_pll3_vcodiv_rate(void)258 u32 cgc1_pll3_vcodiv_rate(void)
259 {
260 u32 reg, gate, div;
261
262 reg = readl(&cgc1_regs->pll3div_vco);
263 gate = BIT(7) & reg;
264 div = reg & 0x3F;
265
266 return gate ? 0 : decode_pll(PLL3) / (div + 1);
267 }
268
cgc1_pll3_pfd_rate(enum cgc1_clk clk)269 u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk)
270 {
271 u32 index, gate, vld, reg;
272
273 switch (clk) {
274 case PLL3_PFD0:
275 index = 0;
276 break;
277 case PLL3_PFD1:
278 index = 1;
279 break;
280 case PLL3_PFD2:
281 index = 2;
282 break;
283 case PLL3_PFD3:
284 index = 3;
285 break;
286 default:
287 return 0;
288 }
289
290 reg = readl(&cgc1_regs->pll3pfdcfg);
291 gate = reg & (BIT(7) << (index * 8));
292 vld = reg & (BIT(6) << (index * 8));
293
294 if (gate || !vld)
295 return 0;
296
297 return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F);
298 }
299
cgc1_pll3_pfd_div(enum cgc1_clk clk)300 u32 cgc1_pll3_pfd_div(enum cgc1_clk clk)
301 {
302 void __iomem *base;
303 u32 pfd, index, gate, reg;
304
305 switch (clk) {
306 case PLL3_PFD0_DIV1:
307 base = &cgc1_regs->pll3div_pfd0;
308 pfd = PLL3_PFD0;
309 index = 0;
310 break;
311 case PLL3_PFD0_DIV2:
312 base = &cgc1_regs->pll3div_pfd0;
313 pfd = PLL3_PFD0;
314 index = 1;
315 break;
316 case PLL3_PFD1_DIV1:
317 base = &cgc1_regs->pll3div_pfd0;
318 pfd = PLL3_PFD1;
319 index = 2;
320 break;
321 case PLL3_PFD1_DIV2:
322 base = &cgc1_regs->pll3div_pfd0;
323 pfd = PLL3_PFD1;
324 index = 3;
325 break;
326 case PLL3_PFD2_DIV1:
327 base = &cgc1_regs->pll3div_pfd1;
328 pfd = PLL3_PFD2;
329 index = 0;
330 break;
331 case PLL3_PFD2_DIV2:
332 base = &cgc1_regs->pll3div_pfd1;
333 pfd = PLL3_PFD2;
334 index = 1;
335 break;
336 case PLL3_PFD3_DIV1:
337 base = &cgc1_regs->pll3div_pfd1;
338 pfd = PLL3_PFD3;
339 index = 2;
340 break;
341 case PLL3_PFD3_DIV2:
342 base = &cgc1_regs->pll3div_pfd1;
343 pfd = PLL3_PFD3;
344 index = 3;
345 break;
346 default:
347 return 0;
348 }
349
350 reg = readl(base);
351 gate = reg & (BIT(7) << (index * 8));
352
353 if (gate)
354 return 0;
355
356 return cgc1_pll3_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1);
357 }
358
cgc1_sosc_div(enum cgc1_clk clk)359 u32 cgc1_sosc_div(enum cgc1_clk clk)
360 {
361 u32 reg, gate, index;
362
363 switch (clk) {
364 case SOSC:
365 return 24000000;
366 case SOSC_DIV1:
367 index = 0;
368 break;
369 case SOSC_DIV2:
370 index = 1;
371 break;
372 case SOSC_DIV3:
373 index = 2;
374 break;
375 default:
376 return 0;
377 }
378
379 reg = readl(&cgc1_regs->soscdiv);
380 gate = reg & (BIT(7) << (index * 8));
381
382 if (gate)
383 return 0;
384
385 return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
386 }
387
cgc1_fro_div(enum cgc1_clk clk)388 u32 cgc1_fro_div(enum cgc1_clk clk)
389 {
390 u32 reg, gate, vld, index;
391
392 switch (clk) {
393 case FRO:
394 return 192000000;
395 case FRO_DIV1:
396 index = 0;
397 break;
398 case FRO_DIV2:
399 index = 1;
400 break;
401 case FRO_DIV3:
402 index = 2;
403 break;
404 default:
405 return 0;
406 }
407
408 reg = readl(&cgc1_regs->frodiv);
409 gate = reg & (BIT(7) << (index * 8));
410 vld = reg & (BIT(6) << (index * 8));
411
412 if (gate || !vld)
413 return 0;
414
415 return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1);
416 }
417
cgc1_clk_get_rate(enum cgc1_clk clk)418 u32 cgc1_clk_get_rate(enum cgc1_clk clk)
419 {
420 switch (clk) {
421 case SOSC:
422 case SOSC_DIV1:
423 case SOSC_DIV2:
424 case SOSC_DIV3:
425 return cgc1_sosc_div(clk);
426 case FRO:
427 case FRO_DIV1:
428 case FRO_DIV2:
429 case FRO_DIV3:
430 return cgc1_fro_div(clk);
431 case PLL2:
432 return decode_pll(PLL2);
433 case PLL3:
434 return decode_pll(PLL3);
435 case PLL3_VCODIV:
436 return cgc1_pll3_vcodiv_rate();
437 case PLL3_PFD0:
438 case PLL3_PFD1:
439 case PLL3_PFD2:
440 case PLL3_PFD3:
441 return cgc1_pll3_pfd_rate(clk);
442 case PLL3_PFD0_DIV1:
443 case PLL3_PFD0_DIV2:
444 case PLL3_PFD1_DIV1:
445 case PLL3_PFD1_DIV2:
446 case PLL3_PFD2_DIV1:
447 case PLL3_PFD2_DIV2:
448 case PLL3_PFD3_DIV1:
449 case PLL3_PFD3_DIV2:
450 return cgc1_pll3_pfd_div(clk);
451 default:
452 printf("Unsupported cgc1 clock: %d\n", clk);
453 return 0;
454 }
455 }
456