1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/io.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/dma.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/rdc-sema.h>
15 #include <asm/arch/imx-rdc.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/bootm.h>
19 #include <dm.h>
20 #include <env.h>
21 #include <imx_thermal.h>
22 #include <fsl_sec.h>
23 #include <asm/setup.h>
24 #include <linux/delay.h>
25
26 #define IOMUXC_GPR1 0x4
27 #define BM_IOMUXC_GPR1_IRQ 0x1000
28
29 #define GPC_LPCR_A7_BSC 0x0
30 #define GPC_LPCR_M4 0x8
31 #define GPC_SLPCR 0x14
32 #define GPC_PGC_ACK_SEL_A7 0x24
33 #define GPC_IMR1_CORE0 0x30
34 #define GPC_IMR1_CORE1 0x40
35 #define GPC_IMR1_M4 0x50
36 #define GPC_PGC_CPU_MAPPING 0xec
37 #define GPC_PGC_C0_PUPSCR 0x804
38 #define GPC_PGC_SCU_TIMING 0x890
39 #define GPC_PGC_C1_PUPSCR 0x844
40
41 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
42 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
43 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
44 #define BM_SLPCR_EN_DSM 0x80000000
45 #define BM_SLPCR_RBC_EN 0x40000000
46 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
47 #define BM_SLPCR_VSTBY 0x4
48 #define BM_SLPCR_SBYOS 0x2
49 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
50 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
51
52 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
53 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
54
55 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
56
57 #if defined(CONFIG_IMX_THERMAL)
58 static const struct imx_thermal_plat imx7_thermal_plat = {
59 .regs = (void *)ANATOP_BASE_ADDR,
60 .fuse_bank = 3,
61 .fuse_word = 3,
62 };
63
64 U_BOOT_DRVINFO(imx7_thermal) = {
65 .name = "imx_thermal",
66 .plat = &imx7_thermal_plat,
67 };
68 #endif
69
70 #if CONFIG_IS_ENABLED(IMX_RDC)
71 /*
72 * In current design, if any peripheral was assigned to both A7 and M4,
73 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
74 * low power mode. So M4 sleep will cause some peripherals fail to work
75 * at A7 core side. At default, all resources are in domain 0 - 3.
76 *
77 * There are 26 peripherals impacted by this IC issue:
78 * SIM2(sim2/emvsim2)
79 * SIM1(sim1/emvsim1)
80 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
81 * SAI1/SAI2/SAI3
82 * WDOG1/WDOG2/WDOG3/WDOG4
83 * GPT1/GPT2/GPT3/GPT4
84 * PWM1/PWM2/PWM3/PWM4
85 * ENET1/ENET2
86 * Software Workaround:
87 * Here we setup some resources to domain 0 where M4 codes will move
88 * the M4 out of this domain. Then M4 is not able to access them any longer.
89 * This is a workaround for ic issue. So the peripherals are not shared
90 * by them. This way requires the uboot implemented the RDC driver and
91 * set the 26 IPs above to domain 0 only. M4 code will assign resource
92 * to its own domain, if it want to use the resource.
93 */
94 static rdc_peri_cfg_t const resources[] = {
95 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
96 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
97 (RDC_PER_UART1 | RDC_DOMAIN(0)),
98 (RDC_PER_UART2 | RDC_DOMAIN(0)),
99 (RDC_PER_UART3 | RDC_DOMAIN(0)),
100 (RDC_PER_UART4 | RDC_DOMAIN(0)),
101 (RDC_PER_UART5 | RDC_DOMAIN(0)),
102 (RDC_PER_UART6 | RDC_DOMAIN(0)),
103 (RDC_PER_UART7 | RDC_DOMAIN(0)),
104 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
105 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
106 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
107 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
108 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
109 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
110 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
111 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
112 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
113 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
114 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
115 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
116 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
117 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
118 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
119 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
120 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
121 };
122
isolate_resource(void)123 static void isolate_resource(void)
124 {
125 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
126 }
127 #endif
128
129 #if defined(CONFIG_IMX_HAB)
130 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
131 .bank = 1,
132 .word = 3,
133 };
134 #endif
135
is_mx7d(void)136 static bool is_mx7d(void)
137 {
138 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
139 struct fuse_bank *bank = &ocotp->bank[1];
140 struct fuse_bank1_regs *fuse =
141 (struct fuse_bank1_regs *)bank->fuse_regs;
142 int val;
143
144 val = readl(&fuse->tester4);
145 if (val & 1)
146 return false;
147 else
148 return true;
149 }
150
get_cpu_rev(void)151 u32 get_cpu_rev(void)
152 {
153 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
154 ANATOP_BASE_ADDR;
155 u32 reg = readl(&ccm_anatop->digprog);
156 u32 type = (reg >> 16) & 0xff;
157
158 if (!is_mx7d())
159 type = MXC_CPU_MX7S;
160
161 reg &= 0xff;
162 return (type << 12) | reg;
163 }
164
165 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)166 u32 __weak get_board_rev(void)
167 {
168 return get_cpu_rev();
169 }
170 #endif
171
imx_enet_mdio_fixup(void)172 static void imx_enet_mdio_fixup(void)
173 {
174 struct iomuxc_gpr_base_regs *gpr_regs =
175 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
176
177 /*
178 * The management data input/output (MDIO) requires open-drain,
179 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
180 * this feature. So to TO1.1, need to enable open drain by setting
181 * bits GPR0[8:7].
182 */
183
184 if (soc_rev() >= CHIP_REV_1_1) {
185 setbits_le32(&gpr_regs->gpr[0],
186 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
187 }
188 }
189
init_cpu_basic(void)190 static void init_cpu_basic(void)
191 {
192 imx_enet_mdio_fixup();
193
194 #ifdef CONFIG_APBH_DMA
195 /* Start APBH DMA */
196 mxs_dma_init();
197 #endif
198 }
199
200 #ifdef CONFIG_IMX_BOOTAUX
201 /*
202 * Table of mappings of physical mem regions in both
203 * Cortex-A7 and Cortex-M4 address spaces.
204 *
205 * For additional details check sections 2.1.2 and 2.1.3 in
206 * i.MX7Dual Applications Processor Reference Manual
207 *
208 */
209 const struct rproc_att hostmap[] = {
210 /* aux core , host core, size */
211 { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
212 { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
213 { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
214 { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
215 { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
216 { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
217 { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
218 { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
219 { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
220 { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
221 { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
222 { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
223 { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
224 { /* sentinel */ }
225 };
226 #endif
227
228 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
229 /* enable all periherial can be accessed in nosec mode */
init_csu(void)230 static void init_csu(void)
231 {
232 int i = 0;
233
234 for (i = 0; i < CSU_NUM_REGS; i++)
235 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
236 }
237
imx_gpcv2_init(void)238 static void imx_gpcv2_init(void)
239 {
240 u32 val, i;
241
242 /*
243 * Force IOMUXC irq pending, so that the interrupt to GPC can be
244 * used to deassert dsm_request signal when the signal gets
245 * asserted unexpectedly.
246 */
247 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
248 val |= BM_IOMUXC_GPR1_IRQ;
249 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
250
251 /* Initially mask all interrupts */
252 for (i = 0; i < 4; i++) {
253 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
254 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
255 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
256 }
257
258 /* set SCU timing */
259 writel((0x59 << 10) | 0x5B | (0x2 << 20),
260 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
261
262 /* only external IRQs to wake up LPM and core 0/1 */
263 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
264 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
265 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
266
267 /* set C0 power up timming per design requirement */
268 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
269 val &= ~BM_GPC_PGC_CORE_PUPSCR;
270 val |= (0x1A << 7);
271 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
272
273 /* set C1 power up timming per design requirement */
274 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
275 val &= ~BM_GPC_PGC_CORE_PUPSCR;
276 val |= (0x1A << 7);
277 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
278
279 /* dummy ack for time slot by default */
280 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
281 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
282 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
283
284 /* mask M4 DSM trigger */
285 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
286 BM_LPCR_M4_MASK_DSM_TRIGGER,
287 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
288
289 /* set mega/fast mix in A7 domain */
290 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
291
292 /* DSM related settings */
293 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
294 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
295 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
296 BM_SLPCR_REG_BYPASS_COUNT);
297 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
298 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
299
300 /*
301 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
302 * due to hardware design requirement, which is
303 * ~61us, here we use 65us for safe
304 */
305 udelay(65);
306 }
307
arch_cpu_init(void)308 int arch_cpu_init(void)
309 {
310 init_aips();
311
312 init_csu();
313 /* Disable PDE bit of WMCR register */
314 imx_wdog_disable_powerdown();
315
316 init_cpu_basic();
317
318 #if CONFIG_IS_ENABLED(IMX_RDC)
319 isolate_resource();
320 #endif
321
322 init_snvs();
323
324 imx_gpcv2_init();
325
326 return 0;
327 }
328 #else
arch_cpu_init(void)329 int arch_cpu_init(void)
330 {
331 init_cpu_basic();
332
333 return 0;
334 }
335 #endif
336
337 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)338 int arch_misc_init(void)
339 {
340 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
341 struct tag_serialnr serialnr;
342 char serial_string[0x20];
343
344 if (is_mx7d())
345 env_set("soc", "imx7d");
346 else
347 env_set("soc", "imx7s");
348
349 /* Set serial# standard environment variable based on OTP settings */
350 get_board_serial(&serialnr);
351 snprintf(serial_string, sizeof(serial_string), "0x%08x%08x",
352 serialnr.low, serialnr.high);
353 env_set("serial#", serial_string);
354 #endif
355
356 #ifdef CONFIG_FSL_CAAM
357 sec_init();
358 #endif
359
360 return 0;
361 }
362 #endif
363
364 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
365 /*
366 * OCOTP_TESTER
367 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
368 * OCOTP_TESTER describes a unique ID based on silicon wafer
369 * and die X/Y position
370 *
371 * OCOTOP_TESTER offset 0x410
372 * 31:0 fuse 0
373 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
374 *
375 * OCOTP_TESTER1 offset 0x420
376 * 31:24 fuse 1
377 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
378 * 23:16 fuse 1
379 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
380 * 15:11 fuse 1
381 * The wafer number of the wafer on which the device was fabricated/SJC
382 * CHALLENGE/ Unique ID
383 * 10:0 fuse 1
384 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
385 */
get_board_serial(struct tag_serialnr * serialnr)386 void get_board_serial(struct tag_serialnr *serialnr)
387 {
388 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
389 struct fuse_bank *bank = &ocotp->bank[0];
390 struct fuse_bank0_regs *fuse =
391 (struct fuse_bank0_regs *)bank->fuse_regs;
392
393 serialnr->low = fuse->tester0;
394 serialnr->high = fuse->tester1;
395 }
396 #endif
397
set_wdog_reset(struct wdog_regs * wdog)398 void set_wdog_reset(struct wdog_regs *wdog)
399 {
400 u32 reg = readw(&wdog->wcr);
401 /*
402 * Output WDOG_B signal to reset external pmic or POR_B decided by
403 * the board desgin. Without external reset, the peripherals/DDR/
404 * PMIC are not reset, that may cause system working abnormal.
405 */
406 reg = readw(&wdog->wcr);
407 reg |= 1 << 3;
408 /*
409 * WDZST bit is write-once only bit. Align this bit in kernel,
410 * otherwise kernel code will have no chance to set this bit.
411 */
412 reg |= 1 << 0;
413 writew(reg, &wdog->wcr);
414 }
415
s_init(void)416 void s_init(void)
417 {
418 /* clock configuration. */
419 clock_init();
420
421 return;
422 }
423
424 #ifndef CONFIG_SPL_BUILD
425 const struct boot_mode soc_boot_modes[] = {
426 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
427 {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
428 {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
429 {NULL, 0},
430 };
431
boot_mode_getprisec(void)432 int boot_mode_getprisec(void)
433 {
434 struct src *psrc = (struct src *)SRC_BASE_ADDR;
435
436 return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
437 }
438 #endif
439
reset_misc(void)440 void reset_misc(void)
441 {
442 #ifndef CONFIG_SPL_BUILD
443 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
444 lcdif_power_down();
445 #endif
446 #endif
447 }
448