1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/mach-imx/hab.h>
16 #include <asm/setup.h>
17 #include <linux/bitops.h>
18
19 #define PMC0_BASE_ADDR 0x410a1000
20 #define PMC0_CTRL 0x28
21 #define PMC0_CTRL_LDOEN BIT(31)
22 #define PMC0_CTRL_LDOOKDIS BIT(30)
23 #define PMC0_CTRL_PMC1ON BIT(24)
24 #define PMC1_BASE_ADDR 0x40400000
25 #define PMC1_RUN 0x8
26 #define PMC1_STOP 0x10
27 #define PMC1_VLPS 0x14
28 #define PMC1_LDOVL_SHIFT 16
29 #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
30 #define PMC1_LDOVL_900 0x1e
31 #define PMC1_LDOVL_950 0x23
32 #define PMC1_STATUS 0x20
33 #define PMC1_STATUS_LDOVLF BIT(8)
34
35 static char *get_reset_cause(char *);
36
37 #if defined(CONFIG_IMX_HAB)
38 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
39 .bank = 29,
40 .word = 6,
41 };
42 #endif
43
44 #define ROM_VERSION_ADDR 0x80
get_cpu_rev(void)45 u32 get_cpu_rev(void)
46 {
47 /* Check the ROM version for cpu revision */
48 u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
49
50 return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
51 }
52
53 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)54 u32 __weak get_board_rev(void)
55 {
56 return get_cpu_rev();
57 }
58 #endif
59
get_boot_mode(void)60 enum bt_mode get_boot_mode(void)
61 {
62 u32 bt0_cfg = 0;
63
64 bt0_cfg = readl(CMC0_RBASE + 0x40);
65 bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
66
67 if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
68 /* No low power boot */
69 if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
70 return DUAL_BOOT;
71 else
72 return SINGLE_BOOT;
73 }
74
75 return LOW_POWER_BOOT;
76 }
77
arch_cpu_init(void)78 int arch_cpu_init(void)
79 {
80 return 0;
81 }
82
83 #ifdef CONFIG_BOARD_POSTCLK_INIT
board_postclk_init(void)84 int board_postclk_init(void)
85 {
86 return 0;
87 }
88 #endif
89
90 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
91 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
92 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
93 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
94
disable_wdog(u32 wdog_base)95 static void disable_wdog(u32 wdog_base)
96 {
97 u32 val_cs = readl(wdog_base + 0x00);
98
99 if (!(val_cs & 0x80))
100 return;
101
102 dmb();
103 __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
104 __raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
105 dmb();
106
107 if (!(val_cs & 800)) {
108 dmb();
109 __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
110 __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
111 dmb();
112
113 while (!(readl(wdog_base + 0x00) & 0x800));
114 }
115 dmb();
116 __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
117 __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */
118 __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
119 dmb();
120
121 while (!(readl(wdog_base + 0x00) & 0x400));
122 }
123
init_wdog(void)124 void init_wdog(void)
125 {
126 /*
127 * ROM will configure WDOG1, disable it or enable it
128 * depending on FUSE. The update bit is set for reconfigurable.
129 * We have to use unlock sequence to reconfigure it.
130 * WDOG2 is not touched by ROM, so it will have default value
131 * which is enabled. We can directly configure it.
132 * To simplify the codes, we still use same reconfigure
133 * process as WDOG1. Because the update bit is not set for
134 * WDOG2, the unlock sequence won't take effect really.
135 * It actually directly configure the wdog.
136 * In this function, we will disable both WDOG1 and WDOG2,
137 * and set update bit for both. So that kernel can reconfigure them.
138 */
139 disable_wdog(WDG1_RBASE);
140 disable_wdog(WDG2_RBASE);
141 }
142
ldo_mode_is_enabled(void)143 static bool ldo_mode_is_enabled(void)
144 {
145 unsigned int reg;
146
147 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
148 if (reg & PMC0_CTRL_LDOEN)
149 return true;
150 else
151 return false;
152 }
153
154 #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
155 #if defined(CONFIG_LDO_ENABLED_MODE)
init_ldo_mode(void)156 static void init_ldo_mode(void)
157 {
158 unsigned int reg;
159
160 if (ldo_mode_is_enabled())
161 return;
162
163 /* Set LDOOKDIS */
164 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
165
166 /* Set LDOVL to 0.95V in PMC1_RUN */
167 reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
168 reg &= ~PMC1_LDOVL_MASK;
169 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
170 writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
171
172 /* Wait for LDOVLF to be cleared */
173 reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
174 while (reg & PMC1_STATUS_LDOVLF)
175 ;
176
177 /* Set LDOVL to 0.95V in PMC1_STOP */
178 reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
179 reg &= ~PMC1_LDOVL_MASK;
180 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
181 writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
182
183 /* Set LDOVL to 0.90V in PMC1_VLPS */
184 reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
185 reg &= ~PMC1_LDOVL_MASK;
186 reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
187 writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
188
189 /* Set LDOEN bit */
190 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
191
192 /* Set the PMC1ON bit */
193 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
194 }
195 #endif
196
s_init(void)197 void s_init(void)
198 {
199 /* Disable wdog */
200 init_wdog();
201
202 /* clock configuration. */
203 clock_init();
204
205 if (soc_rev() < CHIP_REV_2_0) {
206 /* enable dumb pmic */
207 writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
208 }
209
210 #if defined(CONFIG_LDO_ENABLED_MODE)
211 init_ldo_mode();
212 #endif
213 return;
214 }
215 #endif
216
217 #ifndef CONFIG_ULP_WATCHDOG
reset_cpu(void)218 void reset_cpu(void)
219 {
220 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
221 while (1)
222 ;
223 }
224 #endif
225
226 #if defined(CONFIG_DISPLAY_CPUINFO)
get_imx_type(u32 imxtype)227 const char *get_imx_type(u32 imxtype)
228 {
229 return "7ULP";
230 }
231
print_cpuinfo(void)232 int print_cpuinfo(void)
233 {
234 u32 cpurev;
235 char cause[18];
236
237 cpurev = get_cpu_rev();
238
239 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
240 get_imx_type((cpurev & 0xFF000) >> 12),
241 (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
242 mxc_get_clock(MXC_ARM_CLK) / 1000000);
243
244 printf("Reset cause: %s\n", get_reset_cause(cause));
245
246 printf("Boot mode: ");
247 switch (get_boot_mode()) {
248 case LOW_POWER_BOOT:
249 printf("Low power boot\n");
250 break;
251 case DUAL_BOOT:
252 printf("Dual boot\n");
253 break;
254 case SINGLE_BOOT:
255 default:
256 printf("Single boot\n");
257 break;
258 }
259
260 if (ldo_mode_is_enabled())
261 printf("PMC1: LDO enabled mode\n");
262 else
263 printf("PMC1: LDO bypass mode\n");
264
265 return 0;
266 }
267 #endif
268
269 #define CMC_SRS_TAMPER (1 << 31)
270 #define CMC_SRS_SECURITY (1 << 30)
271 #define CMC_SRS_TZWDG (1 << 29)
272 #define CMC_SRS_JTAG_RST (1 << 28)
273 #define CMC_SRS_CORE1 (1 << 16)
274 #define CMC_SRS_LOCKUP (1 << 15)
275 #define CMC_SRS_SW (1 << 14)
276 #define CMC_SRS_WDG (1 << 13)
277 #define CMC_SRS_PIN_RESET (1 << 8)
278 #define CMC_SRS_WARM (1 << 4)
279 #define CMC_SRS_HVD (1 << 3)
280 #define CMC_SRS_LVD (1 << 2)
281 #define CMC_SRS_POR (1 << 1)
282 #define CMC_SRS_WUP (1 << 0)
283
284 static u32 reset_cause = -1;
285
get_reset_cause(char * ret)286 static char *get_reset_cause(char *ret)
287 {
288 u32 cause1, cause = 0, srs = 0;
289 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
290 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
291
292 if (!ret)
293 return "null";
294
295 srs = readl(reg_srs);
296 cause1 = readl(reg_ssrs);
297 writel(cause1, reg_ssrs);
298
299 reset_cause = cause1;
300
301 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
302
303 switch (cause) {
304 case CMC_SRS_POR:
305 sprintf(ret, "%s", "POR");
306 break;
307 case CMC_SRS_WUP:
308 sprintf(ret, "%s", "WUP");
309 break;
310 case CMC_SRS_WARM:
311 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
312 CMC_SRS_JTAG_RST);
313 switch (cause) {
314 case CMC_SRS_WDG:
315 sprintf(ret, "%s", "WARM-WDG");
316 break;
317 case CMC_SRS_SW:
318 sprintf(ret, "%s", "WARM-SW");
319 break;
320 case CMC_SRS_JTAG_RST:
321 sprintf(ret, "%s", "WARM-JTAG");
322 break;
323 default:
324 sprintf(ret, "%s", "WARM-UNKN");
325 break;
326 }
327 break;
328 default:
329 sprintf(ret, "%s-%X", "UNKN", cause1);
330 break;
331 }
332
333 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
334 return ret;
335 }
336
337 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)338 __weak int board_mmc_get_env_dev(int devno)
339 {
340 return CONFIG_SYS_MMC_ENV_DEV;
341 }
342
mmc_get_env_dev(void)343 int mmc_get_env_dev(void)
344 {
345 int devno = 0;
346 u32 bt1_cfg = 0;
347
348 /* If not boot from sd/mmc, use default value */
349 if (get_boot_mode() == LOW_POWER_BOOT)
350 return CONFIG_SYS_MMC_ENV_DEV;
351
352 bt1_cfg = readl(CMC1_RBASE + 0x40);
353 devno = (bt1_cfg >> 9) & 0x7;
354
355 return board_mmc_get_env_dev(devno);
356 }
357 #endif
358
get_boot_device(void)359 enum boot_device get_boot_device(void)
360 {
361 struct bootrom_sw_info **p =
362 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
363
364 enum boot_device boot_dev = SD1_BOOT;
365 u8 boot_type = (*p)->boot_dev_type;
366 u8 boot_instance = (*p)->boot_dev_instance;
367
368 switch (boot_type) {
369 case BOOT_TYPE_SD:
370 boot_dev = boot_instance + SD1_BOOT;
371 break;
372 case BOOT_TYPE_MMC:
373 boot_dev = boot_instance + MMC1_BOOT;
374 break;
375 case BOOT_TYPE_USB:
376 boot_dev = USB_BOOT;
377 break;
378 default:
379 break;
380 }
381
382 return boot_dev;
383 }
384
385 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
386 /*
387 * OCOTP_CFG (SJC CHALLENGE, Unique ID)
388 * i.MX 7ULP Applications Processor Reference Manual, Rev. 0, 09/2020
389 *
390 * OCOTP_CFG0 offset 0x4B0: 15:0 -> 15:0 bits of Unique ID
391 * OCOTP_CFG1 offset 0x4C0: 15:0 -> 31:16 bits of Unique ID
392 * OCOTP_CFG2 offset 0x4D0: 15:0 -> 47:32 bits of Unique ID
393 * OCOTP_CFG3 offset 0x4E0: 15:0 -> 63:48 bits of Unique ID
394 */
get_board_serial(struct tag_serialnr * serialnr)395 void get_board_serial(struct tag_serialnr *serialnr)
396 {
397 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
398 struct fuse_bank *bank = &ocotp->bank[1];
399 struct fuse_bank1_regs *fuse =
400 (struct fuse_bank1_regs *)bank->fuse_regs;
401
402 serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16);
403 serialnr->high = (fuse->cfg2 & 0xFFFF) + ((fuse->cfg3 & 0xFFFF) << 16);
404 }
405 #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
406