1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: AM64 SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_AM64_HARDWARE_H 8 #define __ASM_ARCH_AM64_HARDWARE_H 9 10 #define CTRL_MMR0_BASE 0x43000000 11 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 12 13 #define PADCFG_MMR1_BASE 0xf0000 14 15 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 16 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 17 18 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380 19 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 20 21 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00 22 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 23 24 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000 25 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 26 27 /* After the cfg mask and shifts have been applied */ 28 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 29 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 30 31 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 32 #define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 33 34 #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 35 36 /* 37 * The CTRL_MMR and PADCFG_MMR memory space is divided into several 38 * equally-spaced partitions, so defining the partition size allows us to 39 * determine register addresses common to those partitions. 40 */ 41 #define CTRL_MMR0_PARTITION_SIZE 0x4000 42 43 /* 44 * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. 45 */ 46 #define CTRLMMR_LOCK_KICK0 0x01008 47 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 48 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) 49 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 50 #define CTRLMMR_LOCK_KICK1 0x0100c 51 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a 52 53 #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 54 55 /* Use Last 2K as Scratch pad */ 56 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 57 58 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ 59