1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <ahci.h>
8 #include <cpu_func.h>
9 #include <init.h>
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
12 #include <linux/mbus.h>
13 #include <asm/io.h>
14 #include <asm/pl310.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include <asm/spl.h>
18 #include <sdhci.h>
19
20 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
21 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
22
23 static struct mbus_win windows[] = {
24 /* SPI */
25 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
27
28 /* NOR */
29 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
30 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
31
32 #ifdef CONFIG_ARMADA_MSYS
33 /* DFX */
34 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
35 #endif
36 };
37
lowlevel_init(void)38 void lowlevel_init(void)
39 {
40 /*
41 * Dummy implementation, we only need LOWLEVEL_INIT
42 * on Armada to configure CP15 in start.S / cpu_init_cp15()
43 */
44 }
45
reset_cpu(void)46 void reset_cpu(void)
47 {
48 struct mvebu_system_registers *reg =
49 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
50
51 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
52 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
53 while (1)
54 ;
55 }
56
mvebu_soc_family(void)57 int mvebu_soc_family(void)
58 {
59 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
60
61 switch (devid) {
62 case SOC_MV78230_ID:
63 case SOC_MV78260_ID:
64 case SOC_MV78460_ID:
65 return MVEBU_SOC_AXP;
66
67 case SOC_88F6720_ID:
68 return MVEBU_SOC_A375;
69
70 case SOC_88F6810_ID:
71 case SOC_88F6820_ID:
72 case SOC_88F6828_ID:
73 return MVEBU_SOC_A38X;
74
75 case SOC_98DX3236_ID:
76 case SOC_98DX3336_ID:
77 case SOC_98DX4251_ID:
78 return MVEBU_SOC_MSYS;
79 }
80
81 return MVEBU_SOC_UNKNOWN;
82 }
83
get_boot_device(void)84 u32 get_boot_device(void)
85 {
86 u32 val;
87 u32 boot_device;
88
89 /*
90 * First check, if UART boot-mode is active. This can only
91 * be done, via the bootrom error register. Here the
92 * MSB marks if the UART mode is active.
93 */
94 val = readl(CONFIG_BOOTROM_ERR_REG);
95 boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
96 debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
97 if (boot_device == BOOTROM_ERR_MODE_UART)
98 return BOOT_DEVICE_UART;
99
100 #ifdef CONFIG_ARMADA_38X
101 /*
102 * If the bootrom error code contains any other than zeros it's an
103 * error condition and the bootROM has fallen back to UART boot
104 */
105 boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
106 if (boot_device)
107 return BOOT_DEVICE_UART;
108 #endif
109
110 /*
111 * Now check the SAR register for the strapped boot-device
112 */
113 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
114 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
115 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
116 switch (boot_device) {
117 #ifdef BOOT_FROM_NAND
118 case BOOT_FROM_NAND:
119 return BOOT_DEVICE_NAND;
120 #endif
121 #ifdef BOOT_FROM_MMC
122 case BOOT_FROM_MMC:
123 case BOOT_FROM_MMC_ALT:
124 return BOOT_DEVICE_MMC1;
125 #endif
126 case BOOT_FROM_UART:
127 #ifdef BOOT_FROM_UART_ALT
128 case BOOT_FROM_UART_ALT:
129 #endif
130 return BOOT_DEVICE_UART;
131 #ifdef BOOT_FROM_SATA
132 case BOOT_FROM_SATA:
133 case BOOT_FROM_SATA_ALT:
134 return BOOT_DEVICE_SATA;
135 #endif
136 case BOOT_FROM_SPI:
137 return BOOT_DEVICE_SPI;
138 default:
139 return BOOT_DEVICE_BOOTROM;
140 };
141 }
142
143 #if defined(CONFIG_DISPLAY_CPUINFO)
144
145 #if defined(CONFIG_ARMADA_375)
146 /* SAR frequency values for Armada 375 */
147 static const struct sar_freq_modes sar_freq_tab[] = {
148 { 0, 0x0, 266, 133, 266 },
149 { 1, 0x0, 333, 167, 167 },
150 { 2, 0x0, 333, 167, 222 },
151 { 3, 0x0, 333, 167, 333 },
152 { 4, 0x0, 400, 200, 200 },
153 { 5, 0x0, 400, 200, 267 },
154 { 6, 0x0, 400, 200, 400 },
155 { 7, 0x0, 500, 250, 250 },
156 { 8, 0x0, 500, 250, 334 },
157 { 9, 0x0, 500, 250, 500 },
158 { 10, 0x0, 533, 267, 267 },
159 { 11, 0x0, 533, 267, 356 },
160 { 12, 0x0, 533, 267, 533 },
161 { 13, 0x0, 600, 300, 300 },
162 { 14, 0x0, 600, 300, 400 },
163 { 15, 0x0, 600, 300, 600 },
164 { 16, 0x0, 666, 333, 333 },
165 { 17, 0x0, 666, 333, 444 },
166 { 18, 0x0, 666, 333, 666 },
167 { 19, 0x0, 800, 400, 267 },
168 { 20, 0x0, 800, 400, 400 },
169 { 21, 0x0, 800, 400, 534 },
170 { 22, 0x0, 900, 450, 300 },
171 { 23, 0x0, 900, 450, 450 },
172 { 24, 0x0, 900, 450, 600 },
173 { 25, 0x0, 1000, 500, 500 },
174 { 26, 0x0, 1000, 500, 667 },
175 { 27, 0x0, 1000, 333, 500 },
176 { 28, 0x0, 400, 400, 400 },
177 { 29, 0x0, 1100, 550, 550 },
178 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
179 };
180 #elif defined(CONFIG_ARMADA_38X)
181 /* SAR frequency values for Armada 38x */
182 static const struct sar_freq_modes sar_freq_tab[] = {
183 { 0x0, 0x0, 666, 333, 333 },
184 { 0x2, 0x0, 800, 400, 400 },
185 { 0x4, 0x0, 1066, 533, 533 },
186 { 0x6, 0x0, 1200, 600, 600 },
187 { 0x8, 0x0, 1332, 666, 666 },
188 { 0xc, 0x0, 1600, 800, 800 },
189 { 0x10, 0x0, 1866, 933, 933 },
190 { 0x13, 0x0, 2000, 1000, 933 },
191 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
192 };
193 #elif defined(CONFIG_ARMADA_MSYS)
194 static const struct sar_freq_modes sar_freq_tab[] = {
195 { 0x0, 0x0, 400, 400, 400 },
196 { 0x2, 0x0, 667, 333, 667 },
197 { 0x3, 0x0, 800, 400, 800 },
198 { 0x5, 0x0, 800, 400, 800 },
199 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
200 };
201 #else
202 /* SAR frequency values for Armada XP */
203 static const struct sar_freq_modes sar_freq_tab[] = {
204 { 0xa, 0x5, 800, 400, 400 },
205 { 0x1, 0x5, 1066, 533, 533 },
206 { 0x2, 0x5, 1200, 600, 600 },
207 { 0x2, 0x9, 1200, 600, 400 },
208 { 0x3, 0x5, 1333, 667, 667 },
209 { 0x4, 0x5, 1500, 750, 750 },
210 { 0x4, 0x9, 1500, 750, 500 },
211 { 0xb, 0x9, 1600, 800, 533 },
212 { 0xb, 0xa, 1600, 800, 640 },
213 { 0xb, 0x5, 1600, 800, 800 },
214 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
215 };
216 #endif
217
get_sar_freq(struct sar_freq_modes * sar_freq)218 void get_sar_freq(struct sar_freq_modes *sar_freq)
219 {
220 u32 val;
221 u32 freq;
222 int i;
223
224 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
225 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
226 #else
227 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
228 #endif
229 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
230 #if defined(SAR2_CPU_FREQ_MASK)
231 /*
232 * Shift CPU0 clock frequency select bit from SAR2 register
233 * into correct position
234 */
235 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
236 >> SAR2_CPU_FREQ_OFFS) << 3;
237 #endif
238 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
239 if (sar_freq_tab[i].val == freq) {
240 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
241 *sar_freq = sar_freq_tab[i];
242 return;
243 #else
244 int k;
245 u8 ffc;
246
247 ffc = (val & SAR_FFC_FREQ_MASK) >>
248 SAR_FFC_FREQ_OFFS;
249 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
250 if (sar_freq_tab[k].ffc == ffc) {
251 *sar_freq = sar_freq_tab[k];
252 return;
253 }
254 }
255 i = k;
256 #endif
257 }
258 }
259
260 /* SAR value not found, return 0 for frequencies */
261 *sar_freq = sar_freq_tab[i - 1];
262 }
263
print_cpuinfo(void)264 int print_cpuinfo(void)
265 {
266 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
267 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
268 struct sar_freq_modes sar_freq;
269
270 puts("SoC: ");
271
272 switch (devid) {
273 case SOC_MV78230_ID:
274 puts("MV78230-");
275 break;
276 case SOC_MV78260_ID:
277 puts("MV78260-");
278 break;
279 case SOC_MV78460_ID:
280 puts("MV78460-");
281 break;
282 case SOC_88F6720_ID:
283 puts("MV88F6720-");
284 break;
285 case SOC_88F6810_ID:
286 puts("MV88F6810-");
287 break;
288 case SOC_88F6820_ID:
289 puts("MV88F6820-");
290 break;
291 case SOC_88F6828_ID:
292 puts("MV88F6828-");
293 break;
294 case SOC_98DX3236_ID:
295 puts("98DX3236-");
296 break;
297 case SOC_98DX3336_ID:
298 puts("98DX3336-");
299 break;
300 case SOC_98DX4251_ID:
301 puts("98DX4251-");
302 break;
303 default:
304 puts("Unknown-");
305 break;
306 }
307
308 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
309 switch (revid) {
310 case 1:
311 puts("A0");
312 break;
313 case 2:
314 puts("B0");
315 break;
316 default:
317 printf("?? (%x)", revid);
318 break;
319 }
320 }
321
322 if (mvebu_soc_family() == MVEBU_SOC_A375) {
323 switch (revid) {
324 case MV_88F67XX_A0_ID:
325 puts("A0");
326 break;
327 default:
328 printf("?? (%x)", revid);
329 break;
330 }
331 }
332
333 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
334 switch (revid) {
335 case MV_88F68XX_Z1_ID:
336 puts("Z1");
337 break;
338 case MV_88F68XX_A0_ID:
339 puts("A0");
340 break;
341 case MV_88F68XX_B0_ID:
342 puts("B0");
343 break;
344 default:
345 printf("?? (%x)", revid);
346 break;
347 }
348 }
349
350 if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
351 switch (revid) {
352 case 3:
353 puts("A0");
354 break;
355 case 4:
356 puts("A1");
357 break;
358 default:
359 printf("?? (%x)", revid);
360 break;
361 }
362 }
363
364 get_sar_freq(&sar_freq);
365 printf(" at %d MHz\n", sar_freq.p_clk);
366
367 return 0;
368 }
369 #endif /* CONFIG_DISPLAY_CPUINFO */
370
371 /*
372 * This function initialize Controller DRAM Fastpath windows.
373 * It takes the CS size information from the 0x1500 scratch registers
374 * and sets the correct windows sizes and base addresses accordingly.
375 *
376 * These values are set in the scratch registers by the Marvell
377 * DDR3 training code, which is executed by the SPL before the
378 * main payload (U-Boot) is executed.
379 */
update_sdram_window_sizes(void)380 static void update_sdram_window_sizes(void)
381 {
382 u64 base = 0;
383 u32 size, temp;
384 int i;
385
386 for (i = 0; i < SDRAM_MAX_CS; i++) {
387 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
388 if (size != 0) {
389 size |= ~(SDRAM_ADDR_MASK);
390
391 /* Set Base Address */
392 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
393 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
394
395 /*
396 * Check if out of max window size and resize
397 * the window
398 */
399 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
400 ~(SDRAM_ADDR_MASK)) | 1;
401 temp |= (size & SDRAM_ADDR_MASK);
402 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
403
404 base += ((u64)size + 1);
405 } else {
406 /*
407 * Disable window if not used, otherwise this
408 * leads to overlapping enabled windows with
409 * pretty strange results
410 */
411 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
412 }
413 }
414 }
415
mmu_disable(void)416 void mmu_disable(void)
417 {
418 asm volatile(
419 "mrc p15, 0, r0, c1, c0, 0\n"
420 "bic r0, #1\n"
421 "mcr p15, 0, r0, c1, c0, 0\n");
422 }
423
424 #ifdef CONFIG_ARCH_CPU_INIT
set_cbar(u32 addr)425 static void set_cbar(u32 addr)
426 {
427 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
428 }
429
430 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
431 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
432 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
433 (((addr) & 0xF) << 6))
434 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
435 (((reg) & 0xF) << 2))
436
setup_usb_phys(void)437 static void setup_usb_phys(void)
438 {
439 int dev;
440
441 /*
442 * USB PLL init
443 */
444
445 /* Setup PLL frequency */
446 /* USB REF frequency = 25 MHz */
447 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
448
449 /* Power up PLL and PHY channel */
450 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
451
452 /* Assert VCOCAL_START */
453 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
454
455 mdelay(1);
456
457 /*
458 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
459 */
460
461 for (dev = 0; dev < 3; dev++) {
462 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
463
464 /* Assert REG_RCAL_START in channel REG 1 */
465 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
466 udelay(40);
467 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
468 }
469 }
470
471 /*
472 * This function is not called from the SPL U-Boot version
473 */
arch_cpu_init(void)474 int arch_cpu_init(void)
475 {
476 struct pl310_regs *const pl310 =
477 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
478
479 /*
480 * Only with disabled MMU its possible to switch the base
481 * register address on Armada 38x. Without this the SDRAM
482 * located at >= 0x4000.0000 is also not accessible, as its
483 * still locked to cache.
484 */
485 mmu_disable();
486
487 /* Linux expects the internal registers to be at 0xf1000000 */
488 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
489 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
490
491 /*
492 * From this stage on, the SoC detection is working. As we have
493 * configured the internal register base to the value used
494 * in the macros / defines in the U-Boot header (soc.h).
495 */
496
497 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
498 /*
499 * To fully release / unlock this area from cache, we need
500 * to flush all caches and disable the L2 cache.
501 */
502 icache_disable();
503 dcache_disable();
504 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
505 }
506
507 /*
508 * We need to call mvebu_mbus_probe() before calling
509 * update_sdram_window_sizes() as it disables all previously
510 * configured mbus windows and then configures them as
511 * required for U-Boot. Calling update_sdram_window_sizes()
512 * without this configuration will not work, as the internal
513 * registers can't be accessed reliably because of potenial
514 * double mapping.
515 * After updating the SDRAM access windows we need to call
516 * mvebu_mbus_probe() again, as this now correctly configures
517 * the SDRAM areas that are later used by the MVEBU drivers
518 * (e.g. USB, NETA).
519 */
520
521 /*
522 * First disable all windows
523 */
524 mvebu_mbus_probe(NULL, 0);
525
526 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
527 /*
528 * Now the SDRAM access windows can be reconfigured using
529 * the information in the SDRAM scratch pad registers
530 */
531 update_sdram_window_sizes();
532 }
533
534 /*
535 * Finally the mbus windows can be configured with the
536 * updated SDRAM sizes
537 */
538 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
539
540 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
541 /* Enable GBE0, GBE1, LCD and NFC PUP */
542 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
543 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
544 NAND_PUP_EN | SPI_PUP_EN);
545
546 /* Configure USB PLL and PHYs on AXP */
547 setup_usb_phys();
548 }
549
550 /* Enable NAND and NAND arbiter */
551 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
552
553 /* Disable MBUS error propagation */
554 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
555
556 return 0;
557 }
558 #endif /* CONFIG_ARCH_CPU_INIT */
559
mvebu_get_nand_clock(void)560 u32 mvebu_get_nand_clock(void)
561 {
562 u32 reg;
563
564 if (mvebu_soc_family() == MVEBU_SOC_A38X)
565 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
566 else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
567 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
568 else
569 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
570
571 return CONFIG_SYS_MVEBU_PLL_CLOCK /
572 ((readl(reg) &
573 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
574 }
575
576 /*
577 * SOC specific misc init
578 */
579 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)580 int arch_misc_init(void)
581 {
582 /* Nothing yet, perhaps we need something here later */
583 return 0;
584 }
585 #endif /* CONFIG_ARCH_MISC_INIT */
586
587 #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
board_mmc_init(struct bd_info * bis)588 int board_mmc_init(struct bd_info *bis)
589 {
590 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
591 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
592
593 return 0;
594 }
595 #endif
596
597 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
598 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
599
600 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
601 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
602 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
603
ahci_mvebu_mbus_config(void __iomem * base)604 static void ahci_mvebu_mbus_config(void __iomem *base)
605 {
606 const struct mbus_dram_target_info *dram;
607 int i;
608
609 /* mbus is not initialized in SPL; keep the ROM settings */
610 if (IS_ENABLED(CONFIG_SPL_BUILD))
611 return;
612
613 dram = mvebu_mbus_dram_info();
614
615 for (i = 0; i < 4; i++) {
616 writel(0, base + AHCI_WINDOW_CTRL(i));
617 writel(0, base + AHCI_WINDOW_BASE(i));
618 writel(0, base + AHCI_WINDOW_SIZE(i));
619 }
620
621 for (i = 0; i < dram->num_cs; i++) {
622 const struct mbus_dram_window *cs = dram->cs + i;
623
624 writel((cs->mbus_attr << 8) |
625 (dram->mbus_dram_target_id << 4) | 1,
626 base + AHCI_WINDOW_CTRL(i));
627 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
628 writel(((cs->size - 1) & 0xffff0000),
629 base + AHCI_WINDOW_SIZE(i));
630 }
631 }
632
ahci_mvebu_regret_option(void __iomem * base)633 static void ahci_mvebu_regret_option(void __iomem *base)
634 {
635 /*
636 * Enable the regret bit to allow the SATA unit to regret a
637 * request that didn't receive an acknowlegde and avoid a
638 * deadlock
639 */
640 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
641 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
642 }
643
board_ahci_enable(void)644 int board_ahci_enable(void)
645 {
646 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
647 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
648
649 return 0;
650 }
651
652 #ifdef CONFIG_SCSI_AHCI_PLAT
scsi_init(void)653 void scsi_init(void)
654 {
655 printf("MVEBU SATA INIT\n");
656 board_ahci_enable();
657 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
658 }
659 #endif
660
661 #ifdef CONFIG_USB_XHCI_MVEBU
662 #define USB3_MAX_WINDOWS 4
663 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
664 #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
665
xhci_mvebu_mbus_config(void __iomem * base,const struct mbus_dram_target_info * dram)666 static void xhci_mvebu_mbus_config(void __iomem *base,
667 const struct mbus_dram_target_info *dram)
668 {
669 int i;
670
671 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
672 writel(0, base + USB3_WIN_CTRL(i));
673 writel(0, base + USB3_WIN_BASE(i));
674 }
675
676 for (i = 0; i < dram->num_cs; i++) {
677 const struct mbus_dram_window *cs = dram->cs + i;
678
679 /* Write size, attributes and target id to control register */
680 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
681 (dram->mbus_dram_target_id << 4) | 1,
682 base + USB3_WIN_CTRL(i));
683
684 /* Write base address to base register */
685 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
686 }
687 }
688
board_xhci_enable(fdt_addr_t base)689 int board_xhci_enable(fdt_addr_t base)
690 {
691 const struct mbus_dram_target_info *dram;
692
693 printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
694
695 dram = mvebu_mbus_dram_info();
696 xhci_mvebu_mbus_config((void __iomem *)base, dram);
697
698 return 0;
699 }
700 #endif
701
enable_caches(void)702 void enable_caches(void)
703 {
704 /* Avoid problem with e.g. neta ethernet driver */
705 invalidate_dcache_all();
706
707 /*
708 * Armada 375 still has some problems with d-cache enabled in the
709 * ethernet driver (mvpp2). So lets keep the d-cache disabled
710 * until this is solved.
711 */
712 if (mvebu_soc_family() != MVEBU_SOC_A375) {
713 /* Enable D-cache. I-cache is already enabled in start.S */
714 dcache_enable();
715 }
716 }
717
v7_outer_cache_enable(void)718 void v7_outer_cache_enable(void)
719 {
720 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
721 struct pl310_regs *const pl310 =
722 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
723 u32 u;
724
725 /* The L2 cache is already disabled at this point */
726
727 /*
728 * For Aurora cache in no outer mode, enable via the CP15
729 * coprocessor broadcasting of cache commands to L2.
730 */
731 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
732 u |= BIT(8); /* Set the FW bit */
733 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
734
735 isb();
736
737 /* Enable the L2 cache */
738 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
739 }
740 }
741
v7_outer_cache_disable(void)742 void v7_outer_cache_disable(void)
743 {
744 struct pl310_regs *const pl310 =
745 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
746
747 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
748 }
749