1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Common board functions for AM33XX based boards
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <debug_uart.h>
13 #include <errno.h>
14 #include <init.h>
15 #include <net.h>
16 #include <ns16550.h>
17 #include <omap3_spi.h>
18 #include <spl.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/i2c.h>
26 #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
27 #include <asm/arch/mem-guardian.h>
28 #else
29 #include <asm/arch/mem.h>
30 #endif
31 #include <asm/arch/mmc_host_def.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/global_data.h>
34 #include <asm/io.h>
35 #include <asm/emif.h>
36 #include <asm/gpio.h>
37 #include <asm/omap_common.h>
38 #include <i2c.h>
39 #include <miiphy.h>
40 #include <cpsw.h>
41 #include <linux/delay.h>
42 #include <linux/errno.h>
43 #include <linux/compiler.h>
44 #include <linux/usb/ch9.h>
45 #include <linux/usb/gadget.h>
46 #include <linux/usb/musb.h>
47 #include <asm/omap_musb.h>
48 #include <asm/davinci_rtc.h>
49
50 #define AM43XX_EMIF_BASE 0x4C000000
51 #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
52 #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
53 #define AM43XX_SDRAM_TYPE_SHIFT 29
54 #define AM43XX_SDRAM_TYPE_DDR3 3
55 #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
56 #define AM43XX_RDWRLVLFULL_START 0x80000000
57
58 /* SPI flash. */
59 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
60 #define AM33XX_SPI0_BASE 0x48030000
61 #define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
62 #endif
63
64 DECLARE_GLOBAL_DATA_PTR;
65
dram_init(void)66 int dram_init(void)
67 {
68 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
69 sdram_init();
70 #endif
71
72 /* dram_init must store complete ramsize in gd->ram_size */
73 gd->ram_size = get_ram_size(
74 (void *)CONFIG_SYS_SDRAM_BASE,
75 CONFIG_MAX_RAM_BANK_SIZE);
76 return 0;
77 }
78
dram_init_banksize(void)79 int dram_init_banksize(void)
80 {
81 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
82 gd->bd->bi_dram[0].size = gd->ram_size;
83
84 return 0;
85 }
86
87 #if !CONFIG_IS_ENABLED(OF_CONTROL)
88 static const struct ns16550_plat am33xx_serial[] = {
89 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
90 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
91 # ifdef CONFIG_SYS_NS16550_COM2
92 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
93 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
94 # ifdef CONFIG_SYS_NS16550_COM3
95 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
96 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
97 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
98 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
99 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
100 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
101 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
102 .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
103 # endif
104 # endif
105 };
106
107 U_BOOT_DRVINFOS(am33xx_uarts) = {
108 { "ns16550_serial", &am33xx_serial[0] },
109 # ifdef CONFIG_SYS_NS16550_COM2
110 { "ns16550_serial", &am33xx_serial[1] },
111 # ifdef CONFIG_SYS_NS16550_COM3
112 { "ns16550_serial", &am33xx_serial[2] },
113 { "ns16550_serial", &am33xx_serial[3] },
114 { "ns16550_serial", &am33xx_serial[4] },
115 { "ns16550_serial", &am33xx_serial[5] },
116 # endif
117 # endif
118 };
119
120 #if CONFIG_IS_ENABLED(DM_I2C)
121 static const struct omap_i2c_plat am33xx_i2c[] = {
122 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
123 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
124 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
125 };
126
127 U_BOOT_DRVINFOS(am33xx_i2c) = {
128 { "i2c_omap", &am33xx_i2c[0] },
129 { "i2c_omap", &am33xx_i2c[1] },
130 { "i2c_omap", &am33xx_i2c[2] },
131 };
132 #endif
133
134 #if CONFIG_IS_ENABLED(DM_GPIO)
135 static const struct omap_gpio_plat am33xx_gpio[] = {
136 { 0, AM33XX_GPIO0_BASE },
137 { 1, AM33XX_GPIO1_BASE },
138 { 2, AM33XX_GPIO2_BASE },
139 { 3, AM33XX_GPIO3_BASE },
140 #ifdef CONFIG_AM43XX
141 { 4, AM33XX_GPIO4_BASE },
142 { 5, AM33XX_GPIO5_BASE },
143 #endif
144 };
145
146 U_BOOT_DRVINFOS(am33xx_gpios) = {
147 { "gpio_omap", &am33xx_gpio[0] },
148 { "gpio_omap", &am33xx_gpio[1] },
149 { "gpio_omap", &am33xx_gpio[2] },
150 { "gpio_omap", &am33xx_gpio[3] },
151 #ifdef CONFIG_AM43XX
152 { "gpio_omap", &am33xx_gpio[4] },
153 { "gpio_omap", &am33xx_gpio[5] },
154 #endif
155 };
156 #endif
157 #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
158 static const struct omap3_spi_plat omap3_spi_pdata = {
159 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
160 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
161 };
162
163 U_BOOT_DRVINFO(am33xx_spi) = {
164 .name = "omap3_spi",
165 .plat = &omap3_spi_pdata,
166 };
167 #endif
168 #endif
169
170 #if !CONFIG_IS_ENABLED(DM_GPIO)
171 static const struct gpio_bank gpio_bank_am33xx[] = {
172 { (void *)AM33XX_GPIO0_BASE },
173 { (void *)AM33XX_GPIO1_BASE },
174 { (void *)AM33XX_GPIO2_BASE },
175 { (void *)AM33XX_GPIO3_BASE },
176 #ifdef CONFIG_AM43XX
177 { (void *)AM33XX_GPIO4_BASE },
178 { (void *)AM33XX_GPIO5_BASE },
179 #endif
180 };
181
182 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
183 #endif
184
185 #if defined(CONFIG_MMC_OMAP_HS)
cpu_mmc_init(struct bd_info * bis)186 int cpu_mmc_init(struct bd_info *bis)
187 {
188 int ret;
189
190 ret = omap_mmc_init(0, 0, 0, -1, -1);
191 if (ret)
192 return ret;
193
194 return omap_mmc_init(1, 0, 0, -1, -1);
195 }
196 #endif
197
198 /*
199 * RTC only with DDR in self-refresh mode magic value, checked against during
200 * boot to see if we have a valid config. This should be in sync with the value
201 * that will be in drivers/soc/ti/pm33xx.c.
202 */
203 #define RTC_MAGIC_VAL 0x8cd0
204
205 /* Board type field bit shift for RTC only with DDR in self-refresh mode */
206 #define RTC_BOARD_TYPE_SHIFT 16
207
208 /* AM33XX has two MUSB controllers which can be host or gadget */
209 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
210 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
211 (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
212 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW))
213
214 static struct musb_hdrc_config musb_config = {
215 .multipoint = 1,
216 .dyn_fifo = 1,
217 .num_eps = 16,
218 .ram_bits = 12,
219 };
220
221 #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
222 static struct ti_musb_plat usb0 = {
223 .base = (void *)USB0_OTG_BASE,
224 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
225 .plat = {
226 .config = &musb_config,
227 .power = 50,
228 .platform_ops = &musb_dsps_ops,
229 },
230 };
231
232 static struct ti_musb_plat usb1 = {
233 .base = (void *)USB1_OTG_BASE,
234 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
235 .plat = {
236 .config = &musb_config,
237 .power = 50,
238 .platform_ops = &musb_dsps_ops,
239 },
240 };
241
242 U_BOOT_DRVINFOS(am33xx_usbs) = {
243 #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
244 { "ti-musb-peripheral", &usb0 },
245 #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
246 { "ti-musb-host", &usb0 },
247 #endif
248 #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
249 { "ti-musb-peripheral", &usb1 },
250 #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
251 { "ti-musb-host", &usb1 },
252 #endif
253 };
254
arch_misc_init(void)255 int arch_misc_init(void)
256 {
257 return 0;
258 }
259 #else
260 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
261
262 /* USB 2.0 PHY Control */
263 #define CM_PHY_PWRDN (1 << 0)
264 #define CM_PHY_OTG_PWRDN (1 << 1)
265 #define OTGVDET_EN (1 << 19)
266 #define OTGSESSENDEN (1 << 20)
267
am33xx_usb_set_phy_power(u8 on,u32 * reg_addr)268 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
269 {
270 if (on) {
271 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
272 OTGVDET_EN | OTGSESSENDEN);
273 } else {
274 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
275 }
276 }
277
278 #ifdef CONFIG_AM335X_USB0
am33xx_otg0_set_phy_power(struct udevice * dev,u8 on)279 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
280 {
281 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
282 }
283
284 struct omap_musb_board_data otg0_board_data = {
285 .set_phy_power = am33xx_otg0_set_phy_power,
286 };
287
288 static struct musb_hdrc_platform_data otg0_plat = {
289 .mode = CONFIG_AM335X_USB0_MODE,
290 .config = &musb_config,
291 .power = 50,
292 .platform_ops = &musb_dsps_ops,
293 .board_data = &otg0_board_data,
294 };
295 #endif
296
297 #ifdef CONFIG_AM335X_USB1
am33xx_otg1_set_phy_power(struct udevice * dev,u8 on)298 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
299 {
300 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
301 }
302
303 struct omap_musb_board_data otg1_board_data = {
304 .set_phy_power = am33xx_otg1_set_phy_power,
305 };
306
307 static struct musb_hdrc_platform_data otg1_plat = {
308 .mode = CONFIG_AM335X_USB1_MODE,
309 .config = &musb_config,
310 .power = 50,
311 .platform_ops = &musb_dsps_ops,
312 .board_data = &otg1_board_data,
313 };
314 #endif
315
arch_misc_init(void)316 int arch_misc_init(void)
317 {
318 #ifdef CONFIG_AM335X_USB0
319 musb_register(&otg0_plat, &otg0_board_data,
320 (void *)USB0_OTG_BASE);
321 #endif
322 #ifdef CONFIG_AM335X_USB1
323 musb_register(&otg1_plat, &otg1_board_data,
324 (void *)USB1_OTG_BASE);
325 #endif
326 return 0;
327 }
328 #endif
329
330 #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
331
arch_misc_init(void)332 int arch_misc_init(void)
333 {
334 struct udevice *dev;
335 int ret;
336
337 ret = uclass_first_device(UCLASS_MISC, &dev);
338 if (ret || !dev)
339 return ret;
340
341 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
342 ret = usb_ether_init();
343 if (ret) {
344 pr_err("USB ether init failed\n");
345 return ret;
346 }
347 #endif
348
349 return 0;
350 }
351
352 #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
353
354 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
355
356 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
357 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
rtc32k_unlock(struct davinci_rtc * rtc)358 static void rtc32k_unlock(struct davinci_rtc *rtc)
359 {
360 /*
361 * Unlock the RTC's registers. For more details please see the
362 * RTC_SS section of the TRM. In order to unlock we need to
363 * write these specific values (keys) in this order.
364 */
365 writel(RTC_KICK0R_WE, &rtc->kick0r);
366 writel(RTC_KICK1R_WE, &rtc->kick1r);
367 }
368 #endif
369
370 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
371 /*
372 * Write contents of the RTC_SCRATCH1 register based on board type
373 * Two things are passed
374 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
375 * control gets to kernel, kernel reads the scratchpad register and gets to
376 * know that bootloader has rtc_only support.
377 *
378 * Second important thing is the board type (16:31). This is needed in the
379 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
380 * identify the board type and we go ahead and copy the board strings to
381 * am43xx_board_name.
382 */
update_rtc_magic(void)383 void update_rtc_magic(void)
384 {
385 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
386 u32 magic = RTC_MAGIC_VAL;
387
388 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
389
390 rtc32k_unlock(rtc);
391
392 /* write magic */
393 writel(magic, &rtc->scratch1);
394 }
395 #endif
396
397 /*
398 * In the case of non-SPL based booting we'll want to call these
399 * functions a tiny bit later as it will require gd to be set and cleared
400 * and that's not true in s_init in this case so we cannot do it there.
401 */
board_early_init_f(void)402 int board_early_init_f(void)
403 {
404 set_mux_conf_regs();
405 prcm_init();
406 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
407 update_rtc_magic();
408 #endif
409 return 0;
410 }
411
412 /*
413 * This function is the place to do per-board things such as ramp up the
414 * MPU clock frequency.
415 */
am33xx_spl_board_init(void)416 __weak void am33xx_spl_board_init(void)
417 {
418 }
419
420 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
rtc32k_enable(void)421 static void rtc32k_enable(void)
422 {
423 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
424
425 rtc32k_unlock(rtc);
426
427 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
428 writel((1 << 3) | (1 << 6), &rtc->osc);
429 }
430 #endif
431
uart_soft_reset(void)432 static void uart_soft_reset(void)
433 {
434 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
435 u32 regval;
436
437 regval = readl(&uart_base->uartsyscfg);
438 regval |= UART_RESET;
439 writel(regval, &uart_base->uartsyscfg);
440 while ((readl(&uart_base->uartsyssts) &
441 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
442 ;
443
444 /* Disable smart idle */
445 regval = readl(&uart_base->uartsyscfg);
446 regval |= UART_SMART_IDLE_EN;
447 writel(regval, &uart_base->uartsyscfg);
448 }
449
watchdog_disable(void)450 static void watchdog_disable(void)
451 {
452 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
453
454 writel(0xAAAA, &wdtimer->wdtwspr);
455 while (readl(&wdtimer->wdtwwps) != 0x0)
456 ;
457 writel(0x5555, &wdtimer->wdtwspr);
458 while (readl(&wdtimer->wdtwwps) != 0x0)
459 ;
460 }
461
462 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
463 /*
464 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
465 */
rtc_only(void)466 static void rtc_only(void)
467 {
468 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
469 struct prm_device_inst *prm_device =
470 (struct prm_device_inst *)PRM_DEVICE_INST;
471
472 u32 scratch1, sdrc;
473 void (*resume_func)(void);
474
475 scratch1 = readl(&rtc->scratch1);
476
477 /*
478 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
479 * written to this register when we want to wake up from RTC only
480 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
481 * bits 0-15: RTC_MAGIC_VAL
482 * bits 16-31: board type (needed for sdram_init)
483 */
484 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
485 return;
486
487 rtc32k_unlock(rtc);
488
489 /* Clear RTC magic */
490 writel(0, &rtc->scratch1);
491
492 /*
493 * Update board type based on value stored on RTC_SCRATCH1, this
494 * is done so that we don't need to read the board type from eeprom
495 * over i2c bus which is expensive
496 */
497 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
498
499 /*
500 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
501 * are resuming from self-refresh. This avoids an unnecessary re-init
502 * of the DDR. The re-init takes time and we would need to wait for
503 * it to complete before accessing DDR to avoid L3 NOC errors.
504 */
505 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
506
507 rtc_only_prcm_init();
508 sdram_init();
509
510 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
511 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
512 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
513
514 sdrc &= AM43XX_SDRAM_TYPE_MASK;
515 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
516
517 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
518 writel(AM43XX_RDWRLVLFULL_START,
519 AM43XX_EMIF_BASE +
520 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
521 mdelay(1);
522
523 am43xx_wait:
524 sdrc = readl(AM43XX_EMIF_BASE +
525 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
526 if (sdrc == AM43XX_RDWRLVLFULL_START)
527 goto am43xx_wait;
528 }
529
530 resume_func = (void *)readl(&rtc->scratch0);
531 if (resume_func)
532 resume_func();
533 }
534 #endif
535
s_init(void)536 void s_init(void)
537 {
538 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
539 rtc_only();
540 #endif
541 }
542
early_system_init(void)543 void early_system_init(void)
544 {
545 /*
546 * The ROM will only have set up sufficient pinmux to allow for the
547 * first 4KiB NOR to be read, we must finish doing what we know of
548 * the NOR mux in this space in order to continue.
549 */
550 #ifdef CONFIG_NOR_BOOT
551 enable_norboot_pin_mux();
552 #endif
553 watchdog_disable();
554 set_uart_mux_conf();
555 setup_early_clocks();
556 uart_soft_reset();
557 #ifdef CONFIG_SPL_BUILD
558 /*
559 * Save the boot parameters passed from romcode.
560 * We cannot delay the saving further than this,
561 * to prevent overwrites.
562 */
563 save_omap_boot_params();
564 #endif
565 #ifdef CONFIG_DEBUG_UART_OMAP
566 debug_uart_init();
567 #endif
568
569 #ifdef CONFIG_SPL_BUILD
570 spl_early_init();
571 #endif
572
573 #ifdef CONFIG_TI_I2C_BOARD_DETECT
574 do_board_detect();
575 #endif
576
577 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
578 /* Enable RTC32K clock */
579 rtc32k_enable();
580 #endif
581 }
582
583 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)584 void board_init_f(ulong dummy)
585 {
586 hw_data_init();
587 early_system_init();
588 board_early_init_f();
589 sdram_init();
590 /* dram_init must store complete ramsize in gd->ram_size */
591 gd->ram_size = get_ram_size(
592 (void *)CONFIG_SYS_SDRAM_BASE,
593 CONFIG_MAX_RAM_BANK_SIZE);
594 }
595 #endif
596
597 #endif
598
arch_cpu_init_dm(void)599 int arch_cpu_init_dm(void)
600 {
601 hw_data_init();
602 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
603 early_system_init();
604 #endif
605 return 0;
606 }
607