1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Common board functions for OMAP3 based boards.
5 *
6 * (C) Copyright 2004-2008
7 * Texas Instruments, <www.ti.com>
8 *
9 * Author :
10 * Sunil Kumar <sunilsaini05@gmail.com>
11 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 *
13 * Derived from Beagle Board and 3430 SDP code by
14 * Richard Woodruff <r-woodruff2@ti.com>
15 * Syed Mohammed Khasim <khasim@ti.com>
16 *
17 */
18 #include <common.h>
19 #include <command.h>
20 #include <dm.h>
21 #include <init.h>
22 #include <spl.h>
23 #include <asm/io.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/cache.h>
27 #include <asm/armv7.h>
28 #include <asm/gpio.h>
29 #include <asm/omap_common.h>
30 #include <linux/compiler.h>
31
32 /* Declarations */
33 extern omap3_sysinfo sysinfo;
34 #ifndef CONFIG_SYS_L2CACHE_OFF
35 static void omap3_invalidate_l2_cache_secure(void);
36 #endif
37
38 #if CONFIG_IS_ENABLED(DM_GPIO)
39 #if !CONFIG_IS_ENABLED(OF_CONTROL)
40 /* Manually initialize GPIO banks when OF_CONTROL doesn't */
41 static const struct omap_gpio_plat omap34xx_gpio[] = {
42 { 0, OMAP34XX_GPIO1_BASE },
43 { 1, OMAP34XX_GPIO2_BASE },
44 { 2, OMAP34XX_GPIO3_BASE },
45 { 3, OMAP34XX_GPIO4_BASE },
46 { 4, OMAP34XX_GPIO5_BASE },
47 { 5, OMAP34XX_GPIO6_BASE },
48 };
49
50 U_BOOT_DRVINFOS(omap34xx_gpios) = {
51 { "gpio_omap", &omap34xx_gpio[0] },
52 { "gpio_omap", &omap34xx_gpio[1] },
53 { "gpio_omap", &omap34xx_gpio[2] },
54 { "gpio_omap", &omap34xx_gpio[3] },
55 { "gpio_omap", &omap34xx_gpio[4] },
56 { "gpio_omap", &omap34xx_gpio[5] },
57 };
58 #endif
59 #else
60
61 static const struct gpio_bank gpio_bank_34xx[6] = {
62 { (void *)OMAP34XX_GPIO1_BASE },
63 { (void *)OMAP34XX_GPIO2_BASE },
64 { (void *)OMAP34XX_GPIO3_BASE },
65 { (void *)OMAP34XX_GPIO4_BASE },
66 { (void *)OMAP34XX_GPIO5_BASE },
67 { (void *)OMAP34XX_GPIO6_BASE },
68 };
69
70 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
71
72 #endif
73
early_system_init(void)74 void early_system_init(void)
75 {
76 hw_data_init();
77 }
78
79 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
80 !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
81
82 /******************************************************************************
83 * Routine: secure_unlock
84 * Description: Setup security registers for access
85 * (GP Device only)
86 *****************************************************************************/
secure_unlock_mem(void)87 static void secure_unlock_mem(void)
88 {
89 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
90 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
91 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
92 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
93 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
94
95 /* Protection Module Register Target APE (PM_RT) */
96 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
97 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
98 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
99 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
100
101 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
102 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
103 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
104
105 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
106 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
107 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
108 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
109
110 /* IVA Changes */
111 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
112 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
113 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
114
115 /* SDRC region 0 public */
116 writel(UNLOCK_1, &sms_base->rg_att0);
117 }
118
119 /******************************************************************************
120 * Routine: secureworld_exit()
121 * Description: If chip is EMU and boot type is external
122 * configure secure registers and exit secure world
123 * general use.
124 *****************************************************************************/
secureworld_exit(void)125 static void secureworld_exit(void)
126 {
127 unsigned long i;
128
129 /* configure non-secure access control register */
130 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
131 /* enabling co-processor CP10 and CP11 accesses in NS world */
132 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
133 /*
134 * allow allocation of locked TLBs and L2 lines in NS world
135 * allow use of PLE registers in NS world also
136 */
137 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
138 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
139
140 /* Enable ASA in ACR register */
141 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
142 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
143 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
144
145 /* Exiting secure world */
146 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
147 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
148 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
149 }
150
151 /******************************************************************************
152 * Routine: try_unlock_sram()
153 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
154 * general use.
155 *****************************************************************************/
try_unlock_memory(void)156 static void try_unlock_memory(void)
157 {
158 int mode;
159 int in_sdram = is_running_in_sdram();
160
161 /*
162 * if GP device unlock device SRAM for general use
163 * secure code breaks for Secure/Emulation device - HS/E/T
164 */
165 mode = get_device_type();
166 if (mode == GP_DEVICE)
167 secure_unlock_mem();
168
169 /*
170 * If device is EMU and boot is XIP external booting
171 * Unlock firewalls and disable L2 and put chip
172 * out of secure world
173 *
174 * Assuming memories are unlocked by the demon who put us in SDRAM
175 */
176 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
177 && (!in_sdram)) {
178 secure_unlock_mem();
179 secureworld_exit();
180 }
181
182 return;
183 }
184
185 /******************************************************************************
186 * Routine: s_init
187 * Description: Does early system init of muxing and clocks.
188 * - Called path is with SRAM stack.
189 *****************************************************************************/
s_init(void)190 void s_init(void)
191 {
192 watchdog_init();
193 early_system_init();
194
195 try_unlock_memory();
196
197 #ifndef CONFIG_SYS_L2CACHE_OFF
198 /* Invalidate L2-cache from secure mode */
199 omap3_invalidate_l2_cache_secure();
200 #endif
201
202 set_muxconf_regs();
203 sdelay(100);
204
205 prcm_init();
206
207 per_clocks_enable();
208
209 #ifdef CONFIG_USB_EHCI_OMAP
210 ehci_clocks_enable();
211 #endif
212 }
213 #endif
214
215 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)216 void board_init_f(ulong dummy)
217 {
218 early_system_init();
219 mem_init();
220 /*
221 * Save the boot parameters passed from romcode.
222 * We cannot delay the saving further than this,
223 * to prevent overwrites.
224 */
225 save_omap_boot_params();
226 }
227 #endif
228
229 /*
230 * Routine: misc_init_r
231 * Description: A basic misc_init_r that just displays the die ID
232 */
misc_init_r(void)233 int __weak misc_init_r(void)
234 {
235 omap_die_id_display();
236
237 return 0;
238 }
239
240 /******************************************************************************
241 * Routine: wait_for_command_complete
242 * Description: Wait for posting to finish on watchdog
243 *****************************************************************************/
wait_for_command_complete(struct watchdog * wd_base)244 static void wait_for_command_complete(struct watchdog *wd_base)
245 {
246 int pending = 1;
247 do {
248 pending = readl(&wd_base->wwps);
249 } while (pending);
250 }
251
252 /******************************************************************************
253 * Routine: watchdog_init
254 * Description: Shut down watch dogs
255 *****************************************************************************/
watchdog_init(void)256 void watchdog_init(void)
257 {
258 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
259 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
260
261 /*
262 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
263 * either taken care of by ROM (HS/EMU) or not accessible (GP).
264 * We need to take care of WD2-MPU or take a PRCM reset. WD3
265 * should not be running and does not generate a PRCM reset.
266 */
267
268 setbits_le32(&prcm_base->fclken_wkup, 0x20);
269 setbits_le32(&prcm_base->iclken_wkup, 0x20);
270 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
271
272 writel(WD_UNLOCK1, &wd2_base->wspr);
273 wait_for_command_complete(wd2_base);
274 writel(WD_UNLOCK2, &wd2_base->wspr);
275 }
276
277 /******************************************************************************
278 * Dummy function to handle errors for EABI incompatibility
279 *****************************************************************************/
abort(void)280 void abort(void)
281 {
282 }
283
284 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
285 /******************************************************************************
286 * OMAP3 specific command to switch between NAND HW and SW ecc
287 *****************************************************************************/
do_switch_ecc(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])288 static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
289 char *const argv[])
290 {
291 int hw, strength = 1;
292
293 if (argc < 2 || argc > 3)
294 goto usage;
295
296 if (strncmp(argv[1], "hw", 2) == 0) {
297 hw = 1;
298 if (argc == 3) {
299 if (strncmp(argv[2], "bch8", 4) == 0)
300 strength = 8;
301 else if (strncmp(argv[2], "bch16", 5) == 0)
302 strength = 16;
303 else if (strncmp(argv[2], "hamming", 7) != 0)
304 goto usage;
305 }
306 } else if (strncmp(argv[1], "sw", 2) == 0) {
307 hw = 0;
308 if (argc == 3) {
309 if (strncmp(argv[2], "bch8", 4) == 0)
310 strength = 8;
311 else if (strncmp(argv[2], "hamming", 7) != 0)
312 goto usage;
313 }
314 } else {
315 goto usage;
316 }
317
318 return -omap_nand_switch_ecc(hw, strength);
319
320 usage:
321 printf ("Usage: nandecc %s\n", cmdtp->usage);
322 return 1;
323 }
324
325 U_BOOT_CMD(
326 nandecc, 3, 1, do_switch_ecc,
327 "switch OMAP3 NAND ECC calculation algorithm",
328 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
329 " and 8-bit/16-bit BCH\n"
330 " ecc calculation (second parameter may"
331 " be omitted).\n"
332 "nandecc sw - Switch to NAND software ecc algorithm."
333 );
334
335 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
336
337 #ifdef CONFIG_DISPLAY_BOARDINFO
338 /**
339 * Print board information
340 */
checkboard(void)341 int checkboard (void)
342 {
343 char *mem_s ;
344
345 if (is_mem_sdr())
346 mem_s = "mSDR";
347 else
348 mem_s = "LPDDR";
349
350 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
351 sysinfo.nand_string);
352
353 return 0;
354 }
355 #endif /* CONFIG_DISPLAY_BOARDINFO */
356
omap3_emu_romcode_call(u32 service_id,u32 * parameters)357 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
358 {
359 u32 i, num_params = *parameters;
360 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
361
362 /*
363 * copy the parameters to an un-cached area to avoid coherency
364 * issues
365 */
366 for (i = 0; i < num_params; i++) {
367 __raw_writel(*parameters, sram_scratch_space);
368 parameters++;
369 sram_scratch_space++;
370 }
371
372 /* Now make the PPA call */
373 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
374 }
375
omap3_set_aux_cr_secure(u32 acr)376 void __weak omap3_set_aux_cr_secure(u32 acr)
377 {
378 struct emu_hal_params emu_romcode_params;
379
380 emu_romcode_params.num_params = 1;
381 emu_romcode_params.param1 = acr;
382 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
383 (u32 *)&emu_romcode_params);
384 }
385
v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)386 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
387 u32 cpu_rev_comb, u32 cpu_variant,
388 u32 cpu_rev)
389 {
390 if (get_device_type() == GP_DEVICE)
391 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
392
393 /* L2 Cache Auxiliary Control Register is not banked */
394 }
395
v7_arch_cp15_set_acr(u32 acr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)396 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
397 u32 cpu_variant, u32 cpu_rev)
398 {
399 /* Write ACR - affects secure banked bits */
400 if (get_device_type() == GP_DEVICE)
401 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
402 else
403 omap3_set_aux_cr_secure(acr);
404
405 /* Write ACR - affects non-secure banked bits - some erratas need it */
406 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
407 }
408
409
410 #ifndef CONFIG_SYS_L2CACHE_OFF
omap3_update_aux_cr(u32 set_bits,u32 clear_bits)411 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
412 {
413 u32 acr;
414
415 /* Read ACR */
416 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
417 acr &= ~clear_bits;
418 acr |= set_bits;
419 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
420
421 }
422
423 /* Invalidate the entire L2 cache from secure mode */
omap3_invalidate_l2_cache_secure(void)424 static void omap3_invalidate_l2_cache_secure(void)
425 {
426 if (get_device_type() == GP_DEVICE) {
427 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
428 } else {
429 struct emu_hal_params emu_romcode_params;
430 emu_romcode_params.num_params = 1;
431 emu_romcode_params.param1 = 0;
432 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
433 (u32 *)&emu_romcode_params);
434 }
435 }
436
v7_outer_cache_enable(void)437 void v7_outer_cache_enable(void)
438 {
439
440 /*
441 * Set L2EN
442 * On some revisions L2EN bit is banked on some revisions it's not
443 * No harm in setting both banked bits(in fact this is required
444 * by an erratum)
445 */
446 omap3_update_aux_cr(0x2, 0);
447 }
448
omap3_outer_cache_disable(void)449 void omap3_outer_cache_disable(void)
450 {
451 /*
452 * Clear L2EN
453 * On some revisions L2EN bit is banked on some revisions it's not
454 * No harm in clearing both banked bits(in fact this is required
455 * by an erratum)
456 */
457 omap3_update_aux_cr(0, 0x2);
458 }
459 #endif /* !CONFIG_SYS_L2CACHE_OFF */
460