1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Clock drivers for Qualcomm SDM845
4 *
5 * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
6 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
7 *
8 * Based on Little Kernel driver, simplified
9 */
10
11 #include <common.h>
12 #include <clk-uclass.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include "clock-snapdragon.h"
18
19 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
20
21 struct freq_tbl {
22 uint freq;
23 uint src;
24 u8 pre_div;
25 u16 m;
26 u16 n;
27 };
28
29 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
30 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
31 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
32 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
33 F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
34 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
35 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
36 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
37 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
38 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
39 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
40 F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
41 F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
42 F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
43 F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
44 F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
45 { }
46 };
47
48 static const struct bcr_regs uart2_regs = {
49 .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
50 .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
51 .M = SE9_UART_APPS_M,
52 .N = SE9_UART_APPS_N,
53 .D = SE9_UART_APPS_D,
54 };
55
qcom_find_freq(const struct freq_tbl * f,uint rate)56 const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
57 {
58 if (!f)
59 return NULL;
60
61 if (!f->freq)
62 return f;
63
64 for (; f->freq; f++)
65 if (rate <= f->freq)
66 return f;
67
68 /* Default to our fastest rate */
69 return f - 1;
70 }
71
clk_init_uart(struct msm_clk_priv * priv,uint rate)72 static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
73 {
74 const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
75
76 clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
77 freq->pre_div, freq->m, freq->n, freq->src);
78
79 return 0;
80 }
81
msm_set_rate(struct clk * clk,ulong rate)82 ulong msm_set_rate(struct clk *clk, ulong rate)
83 {
84 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
85
86 switch (clk->id) {
87 case 0x58: /*UART2*/
88 return clk_init_uart(priv, rate);
89 default:
90 return 0;
91 }
92 }
93