1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _CLOCK_MANAGER_H_ 7 #define _CLOCK_MANAGER_H_ 8 9 phys_addr_t socfpga_get_clkmgr_addr(void); 10 11 #ifndef __ASSEMBLY__ 12 void cm_wait_for_lock(u32 mask); 13 int cm_wait_for_fsm(void); 14 void cm_print_clock_quick_summary(void); 15 unsigned long cm_get_mpu_clk_hz(void); 16 unsigned int cm_get_qspi_controller_clk_hz(void); 17 18 #if defined(CONFIG_TARGET_SOCFPGA_SOC64) 19 int cm_set_qspi_controller_clk_hz(u32 clk_hz); 20 #endif 21 #endif 22 23 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 24 #include <asm/arch/clock_manager_gen5.h> 25 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 26 #include <asm/arch/clock_manager_arria10.h> 27 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) 28 #include <asm/arch/clock_manager_s10.h> 29 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) 30 #include <asm/arch/clock_manager_agilex.h> 31 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) 32 #include <asm/arch/clock_manager_n5x.h> 33 #endif 34 35 #endif /* _CLOCK_MANAGER_H_ */ 36