1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2015-2017 Intel Corporation <www.intel.com> 4 */ 5 6 #ifndef _SOCFPGA_SDRAM_ARRIA10_H_ 7 #define _SOCFPGA_SDRAM_ARRIA10_H_ 8 9 #ifndef __ASSEMBLY__ 10 #include <linux/bitops.h> 11 int ddr_calibration_sequence(void); 12 13 struct socfpga_ecc_hmc { 14 u32 ip_rev_id; 15 u32 _pad_0x4_0x7; 16 u32 ddrioctrl; 17 u32 ddrcalstat; 18 u32 mpr_0beat1; 19 u32 mpr_1beat1; 20 u32 mpr_2beat1; 21 u32 mpr_3beat1; 22 u32 mpr_4beat1; 23 u32 mpr_5beat1; 24 u32 mpr_6beat1; 25 u32 mpr_7beat1; 26 u32 mpr_8beat1; 27 u32 mpr_0beat2; 28 u32 mpr_1beat2; 29 u32 mpr_2beat2; 30 u32 mpr_3beat2; 31 u32 mpr_4beat2; 32 u32 mpr_5beat2; 33 u32 mpr_6beat2; 34 u32 mpr_7beat2; 35 u32 mpr_8beat2; 36 u32 _pad_0x58_0x5f[2]; 37 u32 auto_precharge; 38 u32 _pad_0x64_0xff[39]; 39 u32 eccctrl; 40 u32 eccctrl2; 41 u32 _pad_0x108_0x10f[2]; 42 u32 errinten; 43 u32 errintens; 44 u32 errintenr; 45 u32 intmode; 46 u32 intstat; 47 u32 diaginttest; 48 u32 modstat; 49 u32 derraddra; 50 u32 serraddra; 51 u32 _pad_0x134_0x137; 52 u32 autowb_corraddr; 53 u32 serrcntreg; 54 u32 autowb_drop_cntreg; 55 u32 _pad_0x144_0x147; 56 u32 ecc_reg2wreccdatabus; 57 u32 ecc_rdeccdata2regbus; 58 u32 ecc_reg2rdeccdatabus; 59 u32 _pad_0x154_0x15f[3]; 60 u32 ecc_diagon; 61 u32 ecc_decstat; 62 u32 _pad_0x168_0x16f[2]; 63 u32 ecc_errgenaddr_0; 64 u32 ecc_errgenaddr_1; 65 u32 ecc_errgenaddr_2; 66 u32 ecc_errgenaddr_3; 67 }; 68 69 struct socfpga_noc_ddr_scheduler { 70 u32 ddr_t_main_scheduler_id_coreid; 71 u32 ddr_t_main_scheduler_id_revisionid; 72 u32 ddr_t_main_scheduler_ddrconf; 73 u32 ddr_t_main_scheduler_ddrtiming; 74 u32 ddr_t_main_scheduler_ddrmode; 75 u32 ddr_t_main_scheduler_readlatency; 76 u32 _pad_0x20_0x34[8]; 77 u32 ddr_t_main_scheduler_activate; 78 u32 ddr_t_main_scheduler_devtodev; 79 }; 80 81 /* 82 * OCRAM firewall 83 */ 84 struct socfpga_noc_fw_ocram { 85 u32 enable; 86 u32 enable_set; 87 u32 enable_clear; 88 u32 region0; 89 u32 region1; 90 u32 region2; 91 u32 region3; 92 u32 region4; 93 u32 region5; 94 }; 95 96 /* for master such as MPU and FPGA */ 97 struct socfpga_noc_fw_ddr_mpu_fpga2sdram { 98 u32 enable; 99 u32 enable_set; 100 u32 enable_clear; 101 u32 _pad_0xc_0xf; 102 u32 mpuregion0addr; 103 u32 mpuregion1addr; 104 u32 mpuregion2addr; 105 u32 mpuregion3addr; 106 u32 fpga2sdram0region0addr; 107 u32 fpga2sdram0region1addr; 108 u32 fpga2sdram0region2addr; 109 u32 fpga2sdram0region3addr; 110 u32 fpga2sdram1region0addr; 111 u32 fpga2sdram1region1addr; 112 u32 fpga2sdram1region2addr; 113 u32 fpga2sdram1region3addr; 114 u32 fpga2sdram2region0addr; 115 u32 fpga2sdram2region1addr; 116 u32 fpga2sdram2region2addr; 117 u32 fpga2sdram2region3addr; 118 }; 119 120 /* for L3 master */ 121 struct socfpga_noc_fw_ddr_l3 { 122 u32 enable; 123 u32 enable_set; 124 u32 enable_clear; 125 u32 hpsregion0addr; 126 u32 hpsregion1addr; 127 u32 hpsregion2addr; 128 u32 hpsregion3addr; 129 u32 hpsregion4addr; 130 u32 hpsregion5addr; 131 u32 hpsregion6addr; 132 u32 hpsregion7addr; 133 }; 134 135 struct socfpga_io48_mmr { 136 u32 dbgcfg0; 137 u32 dbgcfg1; 138 u32 dbgcfg2; 139 u32 dbgcfg3; 140 u32 dbgcfg4; 141 u32 dbgcfg5; 142 u32 dbgcfg6; 143 u32 reserve0; 144 u32 reserve1; 145 u32 reserve2; 146 u32 ctrlcfg0; 147 u32 ctrlcfg1; 148 u32 ctrlcfg2; 149 u32 ctrlcfg3; 150 u32 ctrlcfg4; 151 u32 ctrlcfg5; 152 u32 ctrlcfg6; 153 u32 ctrlcfg7; 154 u32 ctrlcfg8; 155 u32 ctrlcfg9; 156 u32 dramtiming0; 157 u32 dramodt0; 158 u32 dramodt1; 159 u32 sbcfg0; 160 u32 sbcfg1; 161 u32 sbcfg2; 162 u32 sbcfg3; 163 u32 sbcfg4; 164 u32 sbcfg5; 165 u32 sbcfg6; 166 u32 sbcfg7; 167 u32 caltiming0; 168 u32 caltiming1; 169 u32 caltiming2; 170 u32 caltiming3; 171 u32 caltiming4; 172 u32 caltiming5; 173 u32 caltiming6; 174 u32 caltiming7; 175 u32 caltiming8; 176 u32 caltiming9; 177 u32 caltiming10; 178 u32 dramaddrw; 179 u32 sideband0; 180 u32 sideband1; 181 u32 sideband2; 182 u32 sideband3; 183 u32 sideband4; 184 u32 sideband5; 185 u32 sideband6; 186 u32 sideband7; 187 u32 sideband8; 188 u32 sideband9; 189 u32 sideband10; 190 u32 sideband11; 191 u32 sideband12; 192 u32 sideband13; 193 u32 sideband14; 194 u32 sideband15; 195 u32 dramsts; 196 u32 dbgdone; 197 u32 dbgsignals; 198 u32 dbgreset; 199 u32 dbgmatch; 200 u32 counter0mask; 201 u32 counter1mask; 202 u32 counter0match; 203 u32 counter1match; 204 u32 niosreserve0; 205 u32 niosreserve1; 206 u32 niosreserve2; 207 }; 208 209 #endif /*__ASSEMBLY__ */ 210 211 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000 212 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24 213 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000 214 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19 215 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000 216 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14 217 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00 218 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9 219 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180 220 #define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7 221 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070 222 #define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4 223 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F 224 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0 225 226 #define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM BIT(30) 227 #define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM BIT(29) 228 #define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM BIT(28) 229 #define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM BIT(27) 230 #define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM BIT(26) 231 #define IO48_MMR_CTRLCFG1_DQSTRK_EN BIT(25) 232 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000 233 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19 234 #define IO48_MMR_CTRLCFG1_REORDER_READ BIT(18) 235 #define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA BIT(17) 236 #define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA BIT(16) 237 #define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA BIT(15) 238 #define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA BIT(14) 239 #define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA BIT(13) 240 #define IO48_MMR_CTRLCFG1_REORDER_DATA BIT(12) 241 #define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC BIT(11) 242 #define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC BIT(10) 243 #define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC BIT(9) 244 #define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC BIT(8) 245 #define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC BIT(7) 246 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060 247 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5 248 #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F 249 #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0 250 251 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000 252 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24 253 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000 254 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18 255 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000 256 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12 257 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0 258 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6 259 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F 260 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0 261 262 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000 263 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24 264 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000 265 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18 266 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000 267 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12 268 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0 269 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6 270 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F 271 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0 272 273 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000 274 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24 275 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000 276 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18 277 #define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000 278 #define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12 279 #define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0 280 #define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6 281 #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F 282 #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0 283 284 #define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000 285 #define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24 286 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000 287 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18 288 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000 289 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12 290 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0 291 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6 292 #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F 293 #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0 294 295 #define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000 296 #define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26 297 #define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000 298 #define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18 299 #define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000 300 #define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12 301 #define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0 302 #define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6 303 #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F 304 #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0 305 306 #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF 307 #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0 308 309 #define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000 310 #define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16 311 #define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000 312 #define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14 313 #define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00 314 #define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10 315 #define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0 316 #define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5 317 #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F 318 #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0 319 320 #define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 321 322 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0) 323 #define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK BIT(1) 324 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0) 325 #define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK BIT(1) 326 #define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK BIT(16) 327 #define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) 328 #define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK BIT(8) 329 #define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0) 330 #define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK BIT(8) 331 #define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0) 332 333 #define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8 334 335 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0 336 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6 337 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12 338 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18 339 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21 340 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26 341 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31 342 343 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0 344 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1 345 346 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0 347 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4 348 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10 349 350 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0 351 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2 352 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4 353 354 #define ALT_NOC_FW_DDR_END_ADDR_LSB 16 355 #define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF 356 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0) 357 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK BIT(1) 358 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK BIT(2) 359 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK BIT(3) 360 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK BIT(4) 361 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK BIT(5) 362 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK BIT(6) 363 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK BIT(7) 364 #define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0) 365 #define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK BIT(1) 366 #define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK BIT(2) 367 #define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK BIT(3) 368 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK BIT(4) 369 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK BIT(5) 370 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK BIT(6) 371 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK BIT(7) 372 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK BIT(8) 373 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK BIT(9) 374 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK BIT(10) 375 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK BIT(11) 376 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK BIT(12) 377 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK BIT(13) 378 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK BIT(14) 379 #define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK BIT(15) 380 381 #define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F 382 #endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */ 383