1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/cache.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/cache.h>
16 #include <dm/platdata.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define VERSAL_MEM_MAP_USED 5
21
22 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
23
24 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
25 #define TCM_MAP 1
26 #else
27 #define TCM_MAP 0
28 #endif
29
30 /* +1 is end of list which needs to be empty */
31 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
32
33 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
34 {
35 .virt = 0x80000000UL,
36 .phys = 0x80000000UL,
37 .size = 0x70000000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_NON_SHARE |
40 PTE_BLOCK_PXN | PTE_BLOCK_UXN
41 }, {
42 .virt = 0xf0000000UL,
43 .phys = 0xf0000000UL,
44 .size = 0x0fe00000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 .virt = 0x400000000UL,
50 .phys = 0x400000000UL,
51 .size = 0x200000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_NON_SHARE |
54 PTE_BLOCK_PXN | PTE_BLOCK_UXN
55 }, {
56 .virt = 0x600000000UL,
57 .phys = 0x600000000UL,
58 .size = 0x800000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
60 PTE_BLOCK_INNER_SHARE
61 }, {
62 .virt = 0xe00000000UL,
63 .phys = 0xe00000000UL,
64 .size = 0xf200000000UL,
65 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66 PTE_BLOCK_NON_SHARE |
67 PTE_BLOCK_PXN | PTE_BLOCK_UXN
68 }
69 };
70
mem_map_fill(void)71 void mem_map_fill(void)
72 {
73 int banks = VERSAL_MEM_MAP_USED;
74
75 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
76 versal_mem_map[banks].virt = 0xffe00000UL;
77 versal_mem_map[banks].phys = 0xffe00000UL;
78 versal_mem_map[banks].size = 0x00200000UL;
79 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
80 PTE_BLOCK_INNER_SHARE;
81 banks = banks + 1;
82 #endif
83
84 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
85 /* Zero size means no more DDR that's this is end */
86 if (!gd->bd->bi_dram[i].size)
87 break;
88
89 #if defined(CONFIG_VERSAL_NO_DDR)
90 if (gd->bd->bi_dram[i].start < 0x80000000UL ||
91 gd->bd->bi_dram[i].start > 0x100000000UL) {
92 printf("Ignore caches over %llx/%llx\n",
93 gd->bd->bi_dram[i].start,
94 gd->bd->bi_dram[i].size);
95 continue;
96 }
97 #endif
98 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
99 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
100 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
101 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
102 PTE_BLOCK_INNER_SHARE;
103 banks = banks + 1;
104 }
105 }
106
107 struct mm_region *mem_map = versal_mem_map;
108
get_page_table_size(void)109 u64 get_page_table_size(void)
110 {
111 return 0x14000;
112 }
113
114 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
arm_reserve_mmu(void)115 int arm_reserve_mmu(void)
116 {
117 tcm_init(TCM_LOCK);
118 gd->arch.tlb_size = PGTABLE_SIZE;
119 gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
120
121 return 0;
122 }
123 #endif
124
125 U_BOOT_DRVINFO(soc_xilinx_versal) = {
126 .name = "soc_xilinx_versal",
127 };
128