1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <common.h>
12 #include <cpu_func.h>
13 #include <init.h>
14 #include <watchdog.h>
15
16 #include <asm/immap.h>
17 #include <asm/io.h>
18 #include <asm/rtc.h>
19 #include <linux/compiler.h>
20
cfspi_port_conf(void)21 void cfspi_port_conf(void)
22 {
23 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
24
25 out_8(&gpio->par_dspi,
26 GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
27 GPIO_PAR_DSPI_SCK_SCK);
28 }
29
30 /*
31 * Breath some life into the CPU...
32 *
33 * Set up the memory map,
34 * initialize a bunch of registers,
35 * initialize the UPM's
36 */
cpu_init_f(void)37 void cpu_init_f(void)
38 {
39 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
40 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
41
42 #if !defined(CONFIG_CF_SBF)
43 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
44 pll_t *pll = (pll_t *)MMAP_PLL;
45
46 /* Workaround, must place before fbcs */
47 out_be32(&pll->psr, 0x12);
48
49 out_be32(&scm1->mpr, 0x77777777);
50 out_be32(&scm1->pacra, 0);
51 out_be32(&scm1->pacrb, 0);
52 out_be32(&scm1->pacrc, 0);
53 out_be32(&scm1->pacrd, 0);
54 out_be32(&scm1->pacre, 0);
55 out_be32(&scm1->pacrf, 0);
56 out_be32(&scm1->pacrg, 0);
57 out_be32(&scm1->pacri, 0);
58
59 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
60 && defined(CONFIG_SYS_CS0_CTRL))
61 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
62 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
63 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
64 #endif
65 #endif /* CONFIG_CF_SBF */
66
67 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
68 && defined(CONFIG_SYS_CS1_CTRL))
69 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
70 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
71 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
72 #endif
73
74 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
75 && defined(CONFIG_SYS_CS2_CTRL))
76 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
77 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
78 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
79 #endif
80
81 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
82 && defined(CONFIG_SYS_CS3_CTRL))
83 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
84 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
85 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
86 #endif
87
88 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
89 && defined(CONFIG_SYS_CS4_CTRL))
90 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
91 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
92 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
93 #endif
94
95 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
96 && defined(CONFIG_SYS_CS5_CTRL))
97 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
98 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
99 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
100 #endif
101
102 #ifdef CONFIG_SYS_I2C_FSL
103 out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
104 #endif
105
106 icache_enable();
107
108 cfspi_port_conf();
109 }
110
111 /*
112 * initialize higher level parts of CPU like timers
113 */
cpu_init_r(void)114 int cpu_init_r(void)
115 {
116 #ifdef CONFIG_MCFRTC
117 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
118 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
119
120 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
121 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
122 #endif
123
124 return (0);
125 }
126
uart_port_conf(int port)127 void uart_port_conf(int port)
128 {
129 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
130
131 /* Setup Ports: */
132 switch (port) {
133 case 0:
134 clrbits_be16(&gpio->par_uart,
135 ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
136 setbits_be16(&gpio->par_uart,
137 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
138 break;
139 case 1:
140 clrbits_be16(&gpio->par_uart,
141 ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
142 setbits_be16(&gpio->par_uart,
143 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
144 break;
145 case 2:
146 clrbits_8(&gpio->par_dspi,
147 ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
148 out_8(&gpio->par_dspi,
149 GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
150 break;
151 }
152 }
153