1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2015 Microchip Technology, Inc.
4 * Purna Chandra Mandal, <purna.mandal@microchip.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/clock/microchip,clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "skeleton.dtsi"
11
12/ {
13	compatible = "microchip,pic32mzda", "microchip,pic32mz";
14
15	aliases {
16		gpio0 = &gpioA;
17		gpio1 = &gpioB;
18		gpio2 = &gpioC;
19		gpio3 = &gpioD;
20		gpio4 = &gpioE;
21		gpio5 = &gpioF;
22		gpio6 = &gpioG;
23		gpio7 = &gpioH;
24		gpio8 = &gpioJ;
25		gpio9 = &gpioK;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu@0 {
33			compatible = "mips,mips14kc";
34			device-type = "cpu";
35			reg = <0>;
36		};
37	};
38
39	clock: clk@1f801200 {
40		compatible = "microchip,pic32mzda-clk";
41		reg = <0x1f801200 0x1000>;
42		#clock-cells = <1>;
43	};
44
45	uart1: serial@1f822000 {
46		compatible = "microchip,pic32mzda-uart";
47		reg = <0x1f822000 0x50>;
48		interrupt-parent = <&evic>;
49		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
50		status = "disabled";
51		clocks = <&clock PB2CLK>;
52	};
53
54	uart2: serial@1f822200 {
55		compatible = "microchip,pic32mzda-uart";
56		reg = <0x1f822200 0x50>;
57		interrupt-parent = <&evic>;
58		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
59		clocks = <&clock PB2CLK>;
60		status = "disabled";
61	};
62
63	uart6: serial@1f822a00 {
64		compatible = "microchip,pic32mzda-uart";
65		reg = <0x1f822a00 0x50>;
66		interrupt-parent = <&evic>;
67		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
68		clocks = <&clock PB2CLK>;
69		status = "disabled";
70	};
71
72	evic: interrupt-controller@1f810000 {
73		compatible = "microchip,pic32mzda-evic";
74		interrupt-controller;
75		#interrupt-cells = <2>;
76		reg = <0x1f810000 0x1000>;
77	};
78
79	pinctrl: pinctrl@1f801400 {
80		#address-cells = <1>;
81		#size-cells = <1>;
82		compatible = "microchip,pic32mzda-pinctrl";
83		reg = <0x1f801400 0x100>, /* in  */
84		      <0x1f801500 0x200>, /* out */
85		      <0x1f860000 0xa00>; /* port */
86		reg-names = "ppsin","ppsout","port";
87		status = "disabled";
88
89		gpioA: gpio0@1f860000 {
90			compatible = "microchip,pic32mzda-gpio";
91			reg = <0x1f860000 0xe0>;
92			gpio-controller;
93			#gpio-cells = <2>;
94		};
95
96		gpioB: gpio1@1f860100 {
97			compatible = "microchip,pic32mzda-gpio";
98			reg = <0x1f860100 0xe0>;
99			gpio-controller;
100			#gpio-cells = <2>;
101		};
102
103		gpioC: gpio2@1f860200 {
104			compatible = "microchip,pic32mzda-gpio";
105			reg = <0x1f860200 0xe0>;
106			gpio-controller;
107			#gpio-cells = <2>;
108		};
109
110		gpioD: gpio3@1f860300 {
111			compatible = "microchip,pic32mzda-gpio";
112			reg = <0x1f860300 0xe0>;
113			gpio-controller;
114			#gpio-cells = <2>;
115		};
116
117		gpioE: gpio4@1f860400 {
118			compatible = "microchip,pic32mzda-gpio";
119			reg = <0x1f860400 0xe0>;
120			gpio-controller;
121			#gpio-cells = <2>;
122		};
123
124		gpioF: gpio5@1f860500 {
125			compatible = "microchip,pic32mzda-gpio";
126			reg = <0x1f860500 0xe0>;
127			gpio-controller;
128			#gpio-cells = <2>;
129		};
130
131		gpioG: gpio6@1f860600 {
132			compatible = "microchip,pic32mzda-gpio";
133			reg = <0x1f860600 0xe0>;
134			gpio-controller;
135			#gpio-cells = <2>;
136		};
137
138		gpioH: gpio7@1f860700 {
139			compatible = "microchip,pic32mzda-gpio";
140			reg = <0x1f860700 0xe0>;
141			gpio-controller;
142			#gpio-cells = <2>;
143		};
144
145		gpioJ: gpio9@1f860800 {
146			compatible = "microchip,pic32mzda-gpio";
147			reg = <0x1f860800 0xe0>;
148			gpio-controller;
149			#gpio-cells = <2>;
150		};
151
152		gpioK: gpio10@1f860900 {
153			compatible = "microchip,pic32mzda-gpio";
154			reg = <0x1f860900 0xe0>;
155			gpio-controller;
156			#gpio-cells = <2>;
157		};
158	};
159
160	sdhci: sdhci@1f8ec000 {
161		compatible = "microchip,pic32mzda-sdhci";
162		reg = <0x1f8ec000 0x100>;
163		interrupt-parent = <&evic>;
164		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
165		clocks = <&clock REF4CLK>, <&clock PB5CLK>;
166		clock-names = "base_clk", "sys_clk";
167		clock-freq-min-max = <25000000>,<25000000>;
168		bus-width = <4>;
169		status = "disabled";
170	};
171
172	ethernet: ethernet@1f882000 {
173		compatible = "microchip,pic32mzda-eth";
174		reg = <0x1f882000 0x1000>;
175		interrupt-parent = <&evic>;
176		interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
177		clocks = <&clock PB5CLK>;
178		status = "disabled";
179		#address-cells = <1>;
180		#size-cells = <0>;
181	};
182
183	usb: musb@1f8e3000 {
184		compatible = "microchip,pic32mzda-usb";
185		reg = <0x1f8e3000 0x1000>,
186		      <0x1f884000 0x1000>;
187		reg-names = "mc", "control";
188		interrupt-parent = <&evic>;
189		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
190			     <133 IRQ_TYPE_LEVEL_HIGH>;
191		clocks = <&clock PB5CLK>;
192		clock-names = "usb_clk";
193		status = "disabled";
194	};
195};
196