1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <asm/global_data.h>
12 #include <dm/uclass.h>
13 #include <dt-bindings/clock/mt7628-clk.h>
14 #include <linux/io.h>
15 #include "mt7628.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
set_init_timer_freq(void)19 static void set_init_timer_freq(void)
20 {
21 void __iomem *sysc;
22 u32 bs, val, timer_freq_post;
23
24 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
25
26 /* We can't use the clk driver as the DM has not been initialized yet */
27 bs = readl(sysc + SYSCTL_SYSCFG0_REG);
28 if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) {
29 gd->arch.timer_freq = 25000000;
30 timer_freq_post = 575000000;
31 } else {
32 gd->arch.timer_freq = 40000000;
33 timer_freq_post = 580000000;
34 }
35
36 val = readl(sysc + SYSCTL_CLKCFG0_REG);
37 if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)))
38 gd->arch.timer_freq = timer_freq_post;
39 }
40
mt7628_init(void)41 void mt7628_init(void)
42 {
43 set_init_timer_freq();
44
45 mt7628_ddr_init();
46 }
47
print_cpuinfo(void)48 int print_cpuinfo(void)
49 {
50 void __iomem *sysc;
51 struct udevice *clkdev;
52 u32 val, ver, eco, pkg, ddr, chipmode, ee;
53 ulong cpu_clk, bus_clk, xtal_clk, timer_freq;
54 struct clk clk;
55 int ret;
56
57 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
58
59 val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
60 ver = (val & VER_M) >> VER_S;
61 eco = (val & ECO_M) >> ECO_S;
62 pkg = !!(val & PKG_ID);
63
64 val = readl(sysc + SYSCTL_SYSCFG0_REG);
65 ddr = val & DRAM_TYPE;
66 chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
67
68 val = readl(sysc + SYSCTL_EFUSE_CFG_REG);
69 ee = val & EFUSE_MT7688;
70
71 if (pkg == PKG_ID_KN)
72 ddr = DRAM_DDR1;
73
74 printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n",
75 ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco);
76
77 printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n",
78 ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
79 chipmode & 0x02 ? "XTAL" : "CPLL");
80
81 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk),
82 &clkdev);
83 if (ret)
84 return ret;
85
86 clk.dev = clkdev;
87
88 clk.id = CLK_CPU;
89 cpu_clk = clk_get_rate(&clk);
90
91 clk.id = CLK_SYS;
92 bus_clk = clk_get_rate(&clk);
93
94 clk.id = CLK_XTAL;
95 xtal_clk = clk_get_rate(&clk);
96
97 clk.id = CLK_MIPS_CNT;
98 timer_freq = clk_get_rate(&clk);
99
100 /* Set final timer frequency */
101 if (timer_freq)
102 gd->arch.timer_freq = timer_freq;
103
104 printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n",
105 cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
106
107 return 0;
108 }
109
get_tbclk(void)110 ulong notrace get_tbclk(void)
111 {
112 return gd->arch.timer_freq;
113 }
114