1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
4 * Copyright (C) 2008-2009 MontaVista Software, Inc.
5 *
6 * Authors: Tony Li <tony.li@freescale.com>
7 * Anton Vorontsov <avorontsov@ru.mvista.com>
8 */
9
10 #include <common.h>
11 #include <pci.h>
12 #include <mpc83xx.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define PCIE_MAX_BUSES 2
20
21 static struct {
22 u32 base;
23 u32 size;
24 } mpc83xx_pcie_cfg_space[] = {
25 {
26 .base = CONFIG_SYS_PCIE1_CFG_BASE,
27 .size = CONFIG_SYS_PCIE1_CFG_SIZE,
28 },
29 #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
30 {
31 .base = CONFIG_SYS_PCIE2_CFG_BASE,
32 .size = CONFIG_SYS_PCIE2_CFG_SIZE,
33 },
34 #endif
35 };
36
get_pcie_clk(int index)37 int get_pcie_clk(int index)
38 {
39 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
40 u32 pci_sync_in;
41 u8 spmf;
42 u8 clkin_div;
43 u32 sccr;
44 u32 csb_clk;
45 u32 testval;
46
47 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
48 sccr = im->clk.sccr;
49 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
50 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
51 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
52
53 if (index)
54 testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
55 else
56 testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
57
58 switch (testval) {
59 case 0:
60 return 0;
61 case 1:
62 return csb_clk;
63 case 2:
64 return csb_clk / 2;
65 case 3:
66 return csb_clk / 3;
67 }
68
69 return 0;
70 }
71
mpc83xx_pcie_init_bus(int bus,struct pci_region * reg)72 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
73 {
74 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
75 pex83xx_t *pex = &immr->pciexp[bus];
76 struct pex_outbound_window *out_win;
77 struct pex_inbound_window *in_win;
78 void *hose_cfg_base;
79 unsigned int ram_sz;
80 unsigned int barl;
81 unsigned int tar;
82 u16 reg16;
83 int i;
84
85 /* Enable pex csb bridge inbound & outbound transactions */
86 out_le32(&pex->bridge.pex_csb_ctrl,
87 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
88 PEX_CSB_CTRL_IBPIOE);
89
90 /* Enable bridge outbound */
91 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
92 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
93 PEX_CSB_OBCTRL_CFGWE);
94
95 out_win = &pex->bridge.pex_outbound_win[0];
96 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
97 mpc83xx_pcie_cfg_space[bus].size);
98 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
99 out_le32(&out_win->tarl, 0);
100 out_le32(&out_win->tarh, 0);
101
102 for (i = 0; i < 2; i++) {
103 u32 ar;
104
105 if (reg[i].size == 0)
106 break;
107
108 out_win = &pex->bridge.pex_outbound_win[i + 1];
109 out_le32(&out_win->bar, reg[i].phys_start);
110 out_le32(&out_win->tarl, reg[i].bus_start);
111 out_le32(&out_win->tarh, 0);
112 ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
113 if (reg[i].flags & PCI_REGION_IO)
114 ar |= PEX_OWAR_TYPE_IO;
115 else
116 ar |= PEX_OWAR_TYPE_MEM;
117 out_le32(&out_win->ar, ar);
118 }
119
120 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
121
122 ram_sz = gd->ram_size;
123 barl = 0;
124 tar = 0;
125 i = 0;
126 while (ram_sz > 0) {
127 in_win = &pex->bridge.pex_inbound_win[i];
128 out_le32(&in_win->barl, barl);
129 out_le32(&in_win->barh, 0x0);
130 out_le32(&in_win->tar, tar);
131 if (ram_sz >= 0x10000000) {
132 /* The maxium windows size is 256M */
133 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
134 PEX_IWAR_TYPE_PF | 0x0FFFF000);
135 barl += 0x10000000;
136 tar += 0x10000000;
137 ram_sz -= 0x10000000;
138 } else {
139 /* The UM is not clear here.
140 * So, round up to even Mb boundary */
141
142 ram_sz = ram_sz >> (20 +
143 ((ram_sz & 0xFFFFF) ? 1 : 0));
144 if (!(ram_sz % 2))
145 ram_sz -= 1;
146 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
147 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
148 ram_sz = 0;
149 }
150 i++;
151 }
152
153 in_win = &pex->bridge.pex_inbound_win[i];
154 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
155 out_le32(&in_win->barh, 0);
156 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
157 out_le32(&in_win->ar, PEX_IWAR_EN |
158 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
159
160 /* Enable the host virtual INTX interrupts */
161 out_le32(&pex->bridge.pex_int_axi_misc_enb,
162 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
163
164 /* Hose configure header is memory-mapped */
165 hose_cfg_base = (void *)pex;
166
167 /* Configure the PCIE controller core clock ratio */
168 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
169 ((get_pcie_clk(bus) / 1000000) * 16) / 333);
170 udelay(1000000);
171
172 /* Do Type 1 bridge configuration */
173 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
174 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
175 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
176
177 /*
178 * Write to Command register
179 */
180 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
181 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
182 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
183 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
184
185 /*
186 * Clear non-reserved bits in status register.
187 */
188 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
189 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
190 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
191
192 printf("PCIE%d: ", bus);
193
194 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
195 #define PCI_LTSSM_L0 0x16 /* L0 state */
196 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
197 if (reg16 >= PCI_LTSSM_L0)
198 printf("link\n");
199 else
200 printf("No link\n");
201 }
202
203 /*
204 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
205 * must have been set to cover all of the requested regions.
206 */
mpc83xx_pcie_init(int num_buses,struct pci_region ** reg)207 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
208 {
209 int i;
210
211 /*
212 * Release PCI RST Output signal.
213 * Power on to RST high must be at least 100 ms as per PCI spec.
214 * On warm boots only 1 ms is required, but we play it safe.
215 */
216 udelay(100000);
217
218 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
219 printf("Second PCIE host contoller not configured!\n");
220 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
221 }
222
223 for (i = 0; i < num_buses; i++)
224 mpc83xx_pcie_init_bus(i, reg[i]);
225 }
226