1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 */
8
9 #ifndef CONFIG_CLK_MPC83XX
10
11 #include <common.h>
12 #include <clock_legacy.h>
13 #include <mpc83xx.h>
14 #include <command.h>
15 #include <vsprintf.h>
16 #include <asm/global_data.h>
17 #include <asm/processor.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* ----------------------------------------------------------------- */
22
23 typedef enum {
24 _unk,
25 _off,
26 _byp,
27 _x8,
28 _x4,
29 _x2,
30 _x1,
31 _1x,
32 _1_5x,
33 _2x,
34 _2_5x,
35 _3x
36 } mult_t;
37
38 typedef struct {
39 mult_t core_csb_ratio;
40 mult_t vco_divider;
41 } corecnf_t;
42
43 static corecnf_t corecnf_tab[] = {
44 {_byp, _byp}, /* 0x00 */
45 {_byp, _byp}, /* 0x01 */
46 {_byp, _byp}, /* 0x02 */
47 {_byp, _byp}, /* 0x03 */
48 {_byp, _byp}, /* 0x04 */
49 {_byp, _byp}, /* 0x05 */
50 {_byp, _byp}, /* 0x06 */
51 {_byp, _byp}, /* 0x07 */
52 {_1x, _x2}, /* 0x08 */
53 {_1x, _x4}, /* 0x09 */
54 {_1x, _x8}, /* 0x0A */
55 {_1x, _x8}, /* 0x0B */
56 {_1_5x, _x2}, /* 0x0C */
57 {_1_5x, _x4}, /* 0x0D */
58 {_1_5x, _x8}, /* 0x0E */
59 {_1_5x, _x8}, /* 0x0F */
60 {_2x, _x2}, /* 0x10 */
61 {_2x, _x4}, /* 0x11 */
62 {_2x, _x8}, /* 0x12 */
63 {_2x, _x8}, /* 0x13 */
64 {_2_5x, _x2}, /* 0x14 */
65 {_2_5x, _x4}, /* 0x15 */
66 {_2_5x, _x8}, /* 0x16 */
67 {_2_5x, _x8}, /* 0x17 */
68 {_3x, _x2}, /* 0x18 */
69 {_3x, _x4}, /* 0x19 */
70 {_3x, _x8}, /* 0x1A */
71 {_3x, _x8}, /* 0x1B */
72 };
73
74 /* ----------------------------------------------------------------- */
75
76 /*
77 *
78 */
get_clocks(void)79 int get_clocks(void)
80 {
81 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
82 u32 pci_sync_in;
83 u8 spmf;
84 u8 clkin_div;
85 u32 sccr;
86 u32 corecnf_tab_index;
87 u8 corepll;
88 u32 lcrr;
89
90 u32 csb_clk;
91 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
92 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
93 u32 tsec1_clk;
94 u32 tsec2_clk;
95 u32 usbdr_clk;
96 #elif defined(CONFIG_ARCH_MPC8309)
97 u32 usbdr_clk;
98 #endif
99 #ifdef CONFIG_ARCH_MPC834X
100 u32 usbmph_clk;
101 #endif
102 u32 core_clk;
103 u32 i2c1_clk;
104 #if !defined(CONFIG_ARCH_MPC832X)
105 u32 i2c2_clk;
106 #endif
107 #if defined(CONFIG_FSL_ESDHC)
108 u32 sdhc_clk;
109 #endif
110 #if !defined(CONFIG_ARCH_MPC8309)
111 u32 enc_clk;
112 #endif
113 u32 lbiu_clk;
114 u32 lclk_clk;
115 u32 mem_clk;
116 #if defined(CONFIG_ARCH_MPC8360)
117 u32 mem_sec_clk;
118 #endif
119 #if defined(CONFIG_QE)
120 u32 qepmf;
121 u32 qepdf;
122 u32 qe_clk;
123 u32 brg_clk;
124 #endif
125 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
126 defined(CONFIG_ARCH_MPC837X)
127 u32 pciexp1_clk;
128 u32 pciexp2_clk;
129 #endif
130 #if defined(CONFIG_ARCH_MPC837X)
131 u32 sata_clk;
132 #endif
133
134 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
135 return -1;
136
137 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
138
139 if (im->reset.rcwh & HRCWH_PCI_HOST) {
140 #if defined(CONFIG_SYS_CLK_FREQ)
141 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
142 #else
143 pci_sync_in = 0xDEADBEEF;
144 #endif
145 } else {
146 #if defined(CONFIG_83XX_PCICLK)
147 pci_sync_in = CONFIG_83XX_PCICLK;
148 #else
149 pci_sync_in = 0xDEADBEEF;
150 #endif
151 }
152
153 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
154 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
155
156 sccr = im->clk.sccr;
157
158 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
159 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
160 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
161 case 0:
162 tsec1_clk = 0;
163 break;
164 case 1:
165 tsec1_clk = csb_clk;
166 break;
167 case 2:
168 tsec1_clk = csb_clk / 2;
169 break;
170 case 3:
171 tsec1_clk = csb_clk / 3;
172 break;
173 default:
174 /* unknown SCCR_TSEC1CM value */
175 return -2;
176 }
177 #endif
178
179 #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
180 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
181 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
182 case 0:
183 usbdr_clk = 0;
184 break;
185 case 1:
186 usbdr_clk = csb_clk;
187 break;
188 case 2:
189 usbdr_clk = csb_clk / 2;
190 break;
191 case 3:
192 usbdr_clk = csb_clk / 3;
193 break;
194 default:
195 /* unknown SCCR_USBDRCM value */
196 return -3;
197 }
198 #endif
199
200 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
201 defined(CONFIG_ARCH_MPC837X)
202 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
203 case 0:
204 tsec2_clk = 0;
205 break;
206 case 1:
207 tsec2_clk = csb_clk;
208 break;
209 case 2:
210 tsec2_clk = csb_clk / 2;
211 break;
212 case 3:
213 tsec2_clk = csb_clk / 3;
214 break;
215 default:
216 /* unknown SCCR_TSEC2CM value */
217 return -4;
218 }
219 #elif defined(CONFIG_ARCH_MPC8313)
220 tsec2_clk = tsec1_clk;
221
222 if (!(sccr & SCCR_TSEC1ON))
223 tsec1_clk = 0;
224 if (!(sccr & SCCR_TSEC2ON))
225 tsec2_clk = 0;
226 #endif
227
228 #if defined(CONFIG_ARCH_MPC834X)
229 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
230 case 0:
231 usbmph_clk = 0;
232 break;
233 case 1:
234 usbmph_clk = csb_clk;
235 break;
236 case 2:
237 usbmph_clk = csb_clk / 2;
238 break;
239 case 3:
240 usbmph_clk = csb_clk / 3;
241 break;
242 default:
243 /* unknown SCCR_USBMPHCM value */
244 return -5;
245 }
246
247 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
248 /* if USB MPH clock is not disabled and
249 * USB DR clock is not disabled then
250 * USB MPH & USB DR must have the same rate
251 */
252 return -6;
253 }
254 #endif
255 #if !defined(CONFIG_ARCH_MPC8309)
256 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
257 case 0:
258 enc_clk = 0;
259 break;
260 case 1:
261 enc_clk = csb_clk;
262 break;
263 case 2:
264 enc_clk = csb_clk / 2;
265 break;
266 case 3:
267 enc_clk = csb_clk / 3;
268 break;
269 default:
270 /* unknown SCCR_ENCCM value */
271 return -7;
272 }
273 #endif
274
275 #if defined(CONFIG_FSL_ESDHC)
276 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
277 case 0:
278 sdhc_clk = 0;
279 break;
280 case 1:
281 sdhc_clk = csb_clk;
282 break;
283 case 2:
284 sdhc_clk = csb_clk / 2;
285 break;
286 case 3:
287 sdhc_clk = csb_clk / 3;
288 break;
289 default:
290 /* unknown SCCR_SDHCCM value */
291 return -8;
292 }
293 #endif
294
295 #if defined(CONFIG_ARCH_MPC834X)
296 i2c1_clk = tsec2_clk;
297 #elif defined(CONFIG_ARCH_MPC8360)
298 i2c1_clk = csb_clk;
299 #elif defined(CONFIG_ARCH_MPC832X)
300 i2c1_clk = enc_clk;
301 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
302 i2c1_clk = enc_clk;
303 #elif defined(CONFIG_FSL_ESDHC)
304 i2c1_clk = sdhc_clk;
305 #elif defined(CONFIG_ARCH_MPC837X)
306 i2c1_clk = enc_clk;
307 #elif defined(CONFIG_ARCH_MPC8309)
308 i2c1_clk = csb_clk;
309 #endif
310 #if !defined(CONFIG_ARCH_MPC832X)
311 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
312 #endif
313
314 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
315 defined(CONFIG_ARCH_MPC837X)
316 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
317 case 0:
318 pciexp1_clk = 0;
319 break;
320 case 1:
321 pciexp1_clk = csb_clk;
322 break;
323 case 2:
324 pciexp1_clk = csb_clk / 2;
325 break;
326 case 3:
327 pciexp1_clk = csb_clk / 3;
328 break;
329 default:
330 /* unknown SCCR_PCIEXP1CM value */
331 return -9;
332 }
333
334 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
335 case 0:
336 pciexp2_clk = 0;
337 break;
338 case 1:
339 pciexp2_clk = csb_clk;
340 break;
341 case 2:
342 pciexp2_clk = csb_clk / 2;
343 break;
344 case 3:
345 pciexp2_clk = csb_clk / 3;
346 break;
347 default:
348 /* unknown SCCR_PCIEXP2CM value */
349 return -10;
350 }
351 #endif
352
353 #if defined(CONFIG_ARCH_MPC837X)
354 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
355 case 0:
356 sata_clk = 0;
357 break;
358 case 1:
359 sata_clk = csb_clk;
360 break;
361 case 2:
362 sata_clk = csb_clk / 2;
363 break;
364 case 3:
365 sata_clk = csb_clk / 3;
366 break;
367 default:
368 /* unknown SCCR_SATA1CM value */
369 return -11;
370 }
371 #endif
372
373 lbiu_clk = csb_clk *
374 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
375 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
376 switch (lcrr) {
377 case 2:
378 case 4:
379 case 8:
380 lclk_clk = lbiu_clk / lcrr;
381 break;
382 default:
383 /* unknown lcrr */
384 return -12;
385 }
386
387 mem_clk = csb_clk *
388 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
389 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
390
391 #if defined(CONFIG_ARCH_MPC8360)
392 mem_sec_clk = csb_clk * (1 +
393 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
394 #endif
395
396 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
397 if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
398 /* corecnf_tab_index is too high, possibly wrong value */
399 return -11;
400 }
401 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
402 case _byp:
403 case _x1:
404 case _1x:
405 core_clk = csb_clk;
406 break;
407 case _1_5x:
408 core_clk = (3 * csb_clk) / 2;
409 break;
410 case _2x:
411 core_clk = 2 * csb_clk;
412 break;
413 case _2_5x:
414 core_clk = (5 * csb_clk) / 2;
415 break;
416 case _3x:
417 core_clk = 3 * csb_clk;
418 break;
419 default:
420 /* unknown core to csb ratio */
421 return -13;
422 }
423
424 #if defined(CONFIG_QE)
425 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
426 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
427 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
428 brg_clk = qe_clk / 2;
429 #endif
430
431 gd->arch.csb_clk = csb_clk;
432 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
433 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
434 gd->arch.tsec1_clk = tsec1_clk;
435 gd->arch.tsec2_clk = tsec2_clk;
436 gd->arch.usbdr_clk = usbdr_clk;
437 #elif defined(CONFIG_ARCH_MPC8309)
438 gd->arch.usbdr_clk = usbdr_clk;
439 #endif
440 #if defined(CONFIG_ARCH_MPC834X)
441 gd->arch.usbmph_clk = usbmph_clk;
442 #endif
443 #if defined(CONFIG_FSL_ESDHC)
444 gd->arch.sdhc_clk = sdhc_clk;
445 #endif
446 gd->arch.core_clk = core_clk;
447 gd->arch.i2c1_clk = i2c1_clk;
448 #if !defined(CONFIG_ARCH_MPC832X)
449 gd->arch.i2c2_clk = i2c2_clk;
450 #endif
451 #if !defined(CONFIG_ARCH_MPC8309)
452 gd->arch.enc_clk = enc_clk;
453 #endif
454 gd->arch.lbiu_clk = lbiu_clk;
455 gd->arch.lclk_clk = lclk_clk;
456 gd->mem_clk = mem_clk;
457 #if defined(CONFIG_ARCH_MPC8360)
458 gd->arch.mem_sec_clk = mem_sec_clk;
459 #endif
460 #if defined(CONFIG_QE)
461 gd->arch.qe_clk = qe_clk;
462 gd->arch.brg_clk = brg_clk;
463 #endif
464 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
465 defined(CONFIG_ARCH_MPC837X)
466 gd->arch.pciexp1_clk = pciexp1_clk;
467 gd->arch.pciexp2_clk = pciexp2_clk;
468 #endif
469 #if defined(CONFIG_ARCH_MPC837X)
470 gd->arch.sata_clk = sata_clk;
471 #endif
472 gd->pci_clk = pci_sync_in;
473 gd->cpu_clk = gd->arch.core_clk;
474 gd->bus_clk = gd->arch.csb_clk;
475 return 0;
476
477 }
478
479 /********************************************
480 * get_bus_freq
481 * return system bus freq in Hz
482 *********************************************/
get_bus_freq(ulong dummy)483 ulong get_bus_freq(ulong dummy)
484 {
485 return gd->arch.csb_clk;
486 }
487
488 /********************************************
489 * get_ddr_freq
490 * return ddr bus freq in Hz
491 *********************************************/
get_ddr_freq(ulong dummy)492 ulong get_ddr_freq(ulong dummy)
493 {
494 return gd->mem_clk;
495 }
496
get_serial_clock(void)497 int get_serial_clock(void)
498 {
499 return get_bus_freq(0);
500 }
501
do_clocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])502 static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
503 char *const argv[])
504 {
505 char buf[32];
506
507 printf("Clock configuration:\n");
508 printf(" Core: %-4s MHz\n",
509 strmhz(buf, gd->arch.core_clk));
510 printf(" Coherent System Bus: %-4s MHz\n",
511 strmhz(buf, gd->arch.csb_clk));
512 #if defined(CONFIG_QE)
513 printf(" QE: %-4s MHz\n",
514 strmhz(buf, gd->arch.qe_clk));
515 printf(" BRG: %-4s MHz\n",
516 strmhz(buf, gd->arch.brg_clk));
517 #endif
518 printf(" Local Bus Controller:%-4s MHz\n",
519 strmhz(buf, gd->arch.lbiu_clk));
520 printf(" Local Bus: %-4s MHz\n",
521 strmhz(buf, gd->arch.lclk_clk));
522 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
523 #if defined(CONFIG_ARCH_MPC8360)
524 printf(" DDR Secondary: %-4s MHz\n",
525 strmhz(buf, gd->arch.mem_sec_clk));
526 #endif
527 #if !defined(CONFIG_ARCH_MPC8309)
528 printf(" SEC: %-4s MHz\n",
529 strmhz(buf, gd->arch.enc_clk));
530 #endif
531 printf(" I2C1: %-4s MHz\n",
532 strmhz(buf, gd->arch.i2c1_clk));
533 #if !defined(CONFIG_ARCH_MPC832X)
534 printf(" I2C2: %-4s MHz\n",
535 strmhz(buf, gd->arch.i2c2_clk));
536 #endif
537 #if defined(CONFIG_FSL_ESDHC)
538 printf(" SDHC: %-4s MHz\n",
539 strmhz(buf, gd->arch.sdhc_clk));
540 #endif
541 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
542 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
543 printf(" TSEC1: %-4s MHz\n",
544 strmhz(buf, gd->arch.tsec1_clk));
545 printf(" TSEC2: %-4s MHz\n",
546 strmhz(buf, gd->arch.tsec2_clk));
547 printf(" USB DR: %-4s MHz\n",
548 strmhz(buf, gd->arch.usbdr_clk));
549 #elif defined(CONFIG_ARCH_MPC8309)
550 printf(" USB DR: %-4s MHz\n",
551 strmhz(buf, gd->arch.usbdr_clk));
552 #endif
553 #if defined(CONFIG_ARCH_MPC834X)
554 printf(" USB MPH: %-4s MHz\n",
555 strmhz(buf, gd->arch.usbmph_clk));
556 #endif
557 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
558 defined(CONFIG_ARCH_MPC837X)
559 printf(" PCIEXP1: %-4s MHz\n",
560 strmhz(buf, gd->arch.pciexp1_clk));
561 printf(" PCIEXP2: %-4s MHz\n",
562 strmhz(buf, gd->arch.pciexp2_clk));
563 #endif
564 #if defined(CONFIG_ARCH_MPC837X)
565 printf(" SATA: %-4s MHz\n",
566 strmhz(buf, gd->arch.sata_clk));
567 #endif
568 return 0;
569 }
570
571 U_BOOT_CMD(clocks, 1, 0, do_clocks,
572 "print clock configuration",
573 " clocks"
574 );
575
576 #endif
577