1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
4 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 */
7
8/*  U-Boot - Startup Code for PowerPC based Embedded Boards
9 *
10 *
11 *  The processor starts at 0x00000100 and the code is executed
12 *  from flash. The code is organized to be at an other address
13 *  in memory, but as long we don't jump around before relocating,
14 *  board_init lies at a quite high address and when the cpu has
15 *  jumped there, everything is ok.
16 *  This works because the cpu gives the FLASH (CS0) the whole
17 *  address space at startup, and board_init lies as a echo of
18 *  the flash somewhere up there in the memory map.
19 *
20 *  board_init will change CS0 to be positioned at the correct
21 *  address and (s)dram will be positioned at address 0
22 */
23#include <asm-offsets.h>
24#include <config.h>
25#include <mpc8xx.h>
26
27#include <ppc_asm.tmpl>
28#include <ppc_defs.h>
29
30#include <asm/cache.h>
31#include <asm/mmu.h>
32#include <asm/u-boot.h>
33
34/* We don't want the  MMU yet.
35*/
36#undef	MSR_KERNEL
37#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
38
39/*
40 * Set up GOT: Global Offset Table
41 *
42 * Use r12 to access the GOT
43 */
44	START_GOT
45	GOT_ENTRY(_GOT2_TABLE_)
46	GOT_ENTRY(_FIXUP_TABLE_)
47
48	GOT_ENTRY(_start)
49	GOT_ENTRY(_start_of_vectors)
50	GOT_ENTRY(_end_of_vectors)
51	GOT_ENTRY(transfer_to_handler)
52
53	GOT_ENTRY(__init_end)
54	GOT_ENTRY(__bss_end)
55	GOT_ENTRY(__bss_start)
56	END_GOT
57
58/*
59 * r3 - 1st arg to board_init(): IMMP pointer
60 * r4 - 2nd arg to board_init(): boot flag
61 */
62	.text
63	.long	0x27051956		/* U-Boot Magic Number			*/
64
65	. = EXC_OFF_SYS_RESET
66	.globl	_start
67_start:
68	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
69	mtspr	638, r3
70
71	/* Initialize machine status; enable machine check interrupt		*/
72	/*----------------------------------------------------------------------*/
73	li	r3, MSR_KERNEL		/* Set ME, RI flags */
74	mtmsr	r3
75	mtspr	SRR1, r3		/* Make SRR1 match MSR */
76
77	mfspr	r3, ICR			/* clear Interrupt Cause Register */
78
79	/* Initialize debug port registers					*/
80	/*----------------------------------------------------------------------*/
81	xor	r0, r0, r0		/* Clear R0 */
82	mtspr	LCTRL1, r0		/* Initialize debug port regs */
83	mtspr	LCTRL2, r0
84	mtspr	COUNTA, r0
85	mtspr	COUNTB, r0
86
87	/* Reset the caches							*/
88	/*----------------------------------------------------------------------*/
89
90	mfspr	r3, IC_CST		/* Clear error bits */
91	mfspr	r3, DC_CST
92
93	lis	r3, IDC_UNALL@h		/* Unlock all */
94	mtspr	IC_CST, r3
95	mtspr	DC_CST, r3
96
97	lis	r3, IDC_INVALL@h	/* Invalidate all */
98	mtspr	IC_CST, r3
99	mtspr	DC_CST, r3
100
101	lis	r3, IDC_DISABLE@h	/* Disable data cache */
102	mtspr	DC_CST, r3
103
104	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
105	mtspr	IC_CST, r3
106
107	/* invalidate all tlb's							*/
108	/*----------------------------------------------------------------------*/
109
110	tlbia
111	isync
112
113	/*
114	 * Calculate absolute address in FLASH and jump there
115	 *----------------------------------------------------------------------*/
116
117	lis	r3, CONFIG_SYS_MONITOR_BASE@h
118	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
119	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
120	mtlr	r3
121	blr
122
123in_flash:
124
125	/* initialize some SPRs that are hard to access from C			*/
126	/*----------------------------------------------------------------------*/
127
128	/*
129	 * Disable serialized ifetch and show cycles
130	 * (i.e. set processor to normal mode).
131	 * This is also a silicon bug workaround, see errata
132	 */
133
134	li	r2, 0x0007
135	mtspr	ICTRL, r2
136
137	/* Set up debug mode entry */
138
139	lis	r2, CONFIG_SYS_DER@h
140	ori	r2, r2, CONFIG_SYS_DER@l
141	mtspr	DER, r2
142
143	/* set up the stack on top of internal DPRAM */
144	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
145	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
146	stw	r0, -4(r3)
147	stw	r0, -8(r3)
148	addi	r1, r3, -8
149
150	bl	board_init_f_alloc_reserve
151	addi	r1, r3, -8
152
153	/* Zeroise the CPM dpram */
154	lis	r4, CONFIG_SYS_IMMR@h
155	ori	r4, r4, (0x2000 - 4)
156	li	r0, (0x2000 / 4)
157	mtctr	r0
158	li	r0, 0
1591:	stwu	r0, 4(r4)
160	bdnz	1b
161
162	bl	board_init_f_init_reserve
163
164	/* let the C-code set up the rest					*/
165	/*									*/
166	/* Be careful to keep code relocatable !				*/
167	/*----------------------------------------------------------------------*/
168
169	GET_GOT			/* initialize GOT access			*/
170
171	lis	r3, CONFIG_SYS_IMMR@h
172	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
173
174	bl	board_init_f	/* run 1st part of board init code (from Flash) */
175
176	/* NOTREACHED - board_init_f() does not return */
177
178
179	.globl	_start_of_vectors
180_start_of_vectors:
181
182/* Machine check */
183	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
184
185/* Data Storage exception.  "Never" generated on the 860. */
186	STD_EXCEPTION(0x300, DataStorage, UnknownException)
187
188/* Instruction Storage exception.  "Never" generated on the 860. */
189	STD_EXCEPTION(0x400, InstStorage, UnknownException)
190
191/* External Interrupt exception. */
192	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
193
194/* Alignment exception. */
195	. = 0x600
196Alignment:
197	EXCEPTION_PROLOG(SRR0, SRR1)
198	mfspr	r4,DAR
199	stw	r4,_DAR(r21)
200	mfspr	r5,DSISR
201	stw	r5,_DSISR(r21)
202	addi	r3,r1,STACK_FRAME_OVERHEAD
203	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
204
205/* Program check exception */
206	. = 0x700
207ProgramCheck:
208	EXCEPTION_PROLOG(SRR0, SRR1)
209	addi	r3,r1,STACK_FRAME_OVERHEAD
210	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
211		MSR_KERNEL, COPY_EE)
212
213	/* No FPU on MPC8xx.  This exception is not supposed to happen.
214	*/
215	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
216
217	/* I guess we could implement decrementer, and may have
218	 * to someday for timekeeping.
219	 */
220	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
221	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
222	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
223	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
224	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
225
226	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
227	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
228
229	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
230	 * for all unimplemented and illegal instructions.
231	 */
232	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
233
234	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
235	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
236	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
237	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
238
239	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
240	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
241	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
242	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
243	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
244	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
245	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
246
247	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
248	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
249	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
250	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
251
252
253	.globl	_end_of_vectors
254_end_of_vectors:
255
256
257	. = 0x2000
258
259/*
260 * This code finishes saving the registers to the exception frame
261 * and jumps to the appropriate handler for the exception.
262 * Register r21 is pointer into trap frame, r1 has new stack pointer.
263 */
264	.globl	transfer_to_handler
265transfer_to_handler:
266	stw	r22,_NIP(r21)
267	lis	r22,MSR_POW@h
268	andc	r23,r23,r22
269	stw	r23,_MSR(r21)
270	SAVE_GPR(7, r21)
271	SAVE_4GPRS(8, r21)
272	SAVE_8GPRS(12, r21)
273	SAVE_8GPRS(24, r21)
274	mflr	r23
275	andi.	r24,r23,0x3f00		/* get vector offset */
276	stw	r24,TRAP(r21)
277	li	r22,0
278	stw	r22,RESULT(r21)
279	mtspr	SPRG2,r22		/* r1 is now kernel sp */
280	lwz	r24,0(r23)		/* virtual address of handler */
281	lwz	r23,4(r23)		/* where to go when done */
282	mtspr	SRR0,r24
283	mtspr	SRR1,r20
284	mtlr	r23
285	SYNC
286	rfi				/* jump to handler, enable MMU */
287
288int_return:
289	mfmsr	r28			/* Disable interrupts */
290	li	r4,0
291	ori	r4,r4,MSR_EE
292	andc	r28,r28,r4
293	SYNC				/* Some chip revs need this... */
294	mtmsr	r28
295	SYNC
296	lwz	r2,_CTR(r1)
297	lwz	r0,_LINK(r1)
298	mtctr	r2
299	mtlr	r0
300	lwz	r2,_XER(r1)
301	lwz	r0,_CCR(r1)
302	mtspr	XER,r2
303	mtcrf	0xFF,r0
304	REST_10GPRS(3, r1)
305	REST_10GPRS(13, r1)
306	REST_8GPRS(23, r1)
307	REST_GPR(31, r1)
308	lwz	r2,_NIP(r1)		/* Restore environment */
309	lwz	r0,_MSR(r1)
310	mtspr	SRR0,r2
311	mtspr	SRR1,r0
312	lwz	r0,GPR0(r1)
313	lwz	r2,GPR2(r1)
314	lwz	r1,GPR1(r1)
315	SYNC
316	rfi
317
318/*------------------------------------------------------------------------------*/
319
320/*
321 * void relocate_code(addr_sp, gd, addr_moni)
322 *
323 * This "function" does not return, instead it continues in RAM
324 * after relocating the monitor code.
325 *
326 * r3 = dest
327 * r4 = src
328 * r5 = length in bytes
329 * r6 = cachelinesize
330 */
331	.globl	relocate_code
332relocate_code:
333	mr	r1,  r3		/* Set new stack pointer		*/
334	mr	r9,  r4		/* Save copy of Global Data pointer	*/
335	mr	r10, r5		/* Save copy of Destination Address	*/
336
337	GET_GOT
338	mr	r3,  r5				/* Destination Address	*/
339	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
340	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
341	lwz	r5, GOT(__init_end)
342	sub	r5, r5, r4
343	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
344
345	/*
346	 * Fix GOT pointer:
347	 *
348	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
349	 *
350	 * Offset:
351	 */
352	sub	r15, r10, r4
353
354	/* First our own GOT */
355	add	r12, r12, r15
356	/* then the one used by the C code */
357	add	r30, r30, r15
358
359	/*
360	 * Now relocate code
361	 */
362
363	cmplw	cr1,r3,r4
364	addi	r0,r5,3
365	srwi.	r0,r0,2
366	beq	cr1,4f		/* In place copy is not necessary	*/
367	beq	7f		/* Protect against 0 count		*/
368	mtctr	r0
369	bge	cr1,2f
370
371	la	r8,-4(r4)
372	la	r7,-4(r3)
3731:	lwzu	r0,4(r8)
374	stwu	r0,4(r7)
375	bdnz	1b
376	b	4f
377
3782:	slwi	r0,r0,2
379	add	r8,r4,r0
380	add	r7,r3,r0
3813:	lwzu	r0,-4(r8)
382	stwu	r0,-4(r7)
383	bdnz	3b
384
385/*
386 * Now flush the cache: note that we must start from a cache aligned
387 * address. Otherwise we might miss one cache line.
388 */
3894:	cmpwi	r6,0
390	add	r5,r3,r5
391	beq	7f		/* Always flush prefetch queue in any case */
392	subi	r0,r6,1
393	andc	r3,r3,r0
394	mr	r4,r3
3955:	dcbst	0,r4
396	add	r4,r4,r6
397	cmplw	r4,r5
398	blt	5b
399	sync			/* Wait for all dcbst to complete on bus */
400	mr	r4,r3
4016:	icbi	0,r4
402	add	r4,r4,r6
403	cmplw	r4,r5
404	blt	6b
4057:	sync			/* Wait for all icbi to complete on bus	*/
406	isync
407
408/*
409 * We are done. Do not return, instead branch to second part of board
410 * initialization, now running from RAM.
411 */
412
413	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
414	mtlr	r0
415	blr
416
417in_ram:
418
419	/*
420	 * Relocation Function, r12 point to got2+0x8000
421	 *
422	 * Adjust got2 pointers, no need to check for 0, this code
423	 * already puts a few entries in the table.
424	 */
425	li	r0,__got2_entries@sectoff@l
426	la	r3,GOT(_GOT2_TABLE_)
427	lwz	r11,GOT(_GOT2_TABLE_)
428	mtctr	r0
429	sub	r11,r3,r11
430	addi	r3,r3,-4
4311:	lwzu	r0,4(r3)
432	cmpwi	r0,0
433	beq-	2f
434	add	r0,r0,r11
435	stw	r0,0(r3)
4362:	bdnz	1b
437
438	/*
439	 * Now adjust the fixups and the pointers to the fixups
440	 * in case we need to move ourselves again.
441	 */
442	li	r0,__fixup_entries@sectoff@l
443	lwz	r3,GOT(_FIXUP_TABLE_)
444	cmpwi	r0,0
445	mtctr	r0
446	addi	r3,r3,-4
447	beq	4f
4483:	lwzu	r4,4(r3)
449	lwzux	r0,r4,r11
450	cmpwi	r0,0
451	add	r0,r0,r11
452	stw	r4,0(r3)
453	beq-	5f
454	stw	r0,0(r4)
4555:	bdnz	3b
4564:
457clear_bss:
458	/*
459	 * Now clear BSS segment
460	 */
461	lwz	r3,GOT(__bss_start)
462	lwz	r4,GOT(__bss_end)
463
464	cmplw	0, r3, r4
465	beq	6f
466
467	li	r0, 0
4685:
469	stw	r0, 0(r3)
470	addi	r3, r3, 4
471	cmplw	0, r3, r4
472	bne	5b
4736:
474
475	mr	r3, r9		/* Global Data pointer		*/
476	mr	r4, r10		/* Destination Address		*/
477	bl	board_init_r
478
479	/*
480	 * Copy exception vector code to low memory
481	 *
482	 * r3: dest_addr
483	 * r7: source address, r8: end address, r9: target address
484	 */
485	.globl	trap_init
486trap_init:
487	mflr	r4			/* save link register		*/
488	GET_GOT
489	lwz	r7, GOT(_start)
490	lwz	r8, GOT(_end_of_vectors)
491
492	li	r9, 0x100		/* reset vector always at 0x100 */
493
494	cmplw	0, r7, r8
495	bgelr				/* return if r7>=r8 - just in case */
4961:
497	lwz	r0, 0(r7)
498	stw	r0, 0(r9)
499	addi	r7, r7, 4
500	addi	r9, r9, 4
501	cmplw	0, r7, r8
502	bne	1b
503
504	/*
505	 * relocate `hdlr' and `int_return' entries
506	 */
507	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
508	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
5092:
510	bl	trap_reloc
511	addi	r7, r7, 0x100		/* next exception vector	*/
512	cmplw	0, r7, r8
513	blt	2b
514
515	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
516	bl	trap_reloc
517
518	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
519	bl	trap_reloc
520
521	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
522	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
5233:
524	bl	trap_reloc
525	addi	r7, r7, 0x100		/* next exception vector	*/
526	cmplw	0, r7, r8
527	blt	3b
528
529	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
530	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
5314:
532	bl	trap_reloc
533	addi	r7, r7, 0x100		/* next exception vector	*/
534	cmplw	0, r7, r8
535	blt	4b
536
537	mtlr	r4			/* restore link register	*/
538	blr
539