1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P5040 Silicon/SoC Device Tree Source (pre include)
4 *
5 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019-2020 NXP
7 */
8
9/dts-v1/;
10
11/include/ "e5500_power_isa.dtsi"
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: PowerPC,e5500@0 {
23			device_type = "cpu";
24			reg = <0>;
25			fsl,portid-mapping = <0x80000000>;
26		};
27		cpu1: PowerPC,e5500@1 {
28			device_type = "cpu";
29			reg = <1>;
30			fsl,portid-mapping = <0x40000000>;
31		};
32		cpu2: PowerPC,e5500@2 {
33			device_type = "cpu";
34			reg = <2>;
35			fsl,portid-mapping = <0x20000000>;
36		};
37		cpu3: PowerPC,e5500@3 {
38			device_type = "cpu";
39			reg = <3>;
40			fsl,portid-mapping = <0x10000000>;
41		};
42	};
43
44	soc: soc@ffe000000 {
45		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
46		reg = <0xf 0xfe000000 0 0x00001000>;
47		#address-cells = <1>;
48		#size-cells = <1>;
49		device_type = "soc";
50		compatible = "simple-bus";
51
52		mpic: pic@40000 {
53			interrupt-controller;
54			#address-cells = <0>;
55			#interrupt-cells = <4>;
56			reg = <0x40000 0x40000>;
57			compatible = "fsl,mpic", "chrp,open-pic";
58			device_type = "open-pic";
59			clock-frequency = <0x0>;
60		};
61
62		espi0: spi@110000 {
63			compatible = "fsl,mpc8536-espi";
64			#address-cells = <1>;
65			#size-cells = <0>;
66			reg = <0x110000 0x1000>;
67			fsl,espi-num-chipselects = <4>;
68			status = "disabled";
69		};
70
71		usb@210000 {
72			compatible = "fsl-usb2-mph";
73			reg = <0x210000 0x1000>;
74			phy_type = "utmi";
75		};
76
77		usb@211000 {
78			compatible = "fsl-usb2-dr";
79			reg = <0x211000 0x1000>;
80			phy_type = "utmi";
81		};
82
83		sata: sata@220000 {
84			compatible = "fsl,pq-sata-v2";
85			reg = <0x220000 0x1000>;
86			interrupts = <68 0x2 0 0>;
87			sata-offset = <0x1000>;
88			sata-number = <2>;
89			sata-fpdma = <0>;
90		};
91
92		esdhc: esdhc@114000 {
93			compatible = "fsl,esdhc";
94			reg = <0x114000 0x1000>;
95			clock-frequency = <0>;
96		};
97
98		/include/ "qoriq-i2c-0.dtsi"
99		/include/ "qoriq-i2c-1.dtsi"
100	};
101
102	pcie@ffe200000 {
103		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
104		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
105		law_trgt_if = <0>;
106		#address-cells = <3>;
107		#size-cells = <2>;
108		device_type = "pci";
109		bus-range = <0x0 0xff>;
110		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
111			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
112	};
113
114	pcie@ffe201000 {
115		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
116		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
117		law_trgt_if = <1>;
118		#address-cells = <3>;
119		#size-cells = <2>;
120		device_type = "pci";
121		bus-range = <0x0 0xff>;
122		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
123			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
124	};
125
126	pcie@ffe202000 {
127		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
128		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
129		law_trgt_if = <2>;
130		#address-cells = <3>;
131		#size-cells = <2>;
132		device_type = "pci";
133		bus-range = <0x0 0xff>;
134		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
135			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
136	};
137};
138