1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T4240RDB Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019-2021 NXP
7 */
8
9/include/ "t4240.dtsi"
10
11/ {
12	model = "fsl,T4240RDB";
13	compatible = "fsl,T4240RDB";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&mpic>;
17
18	aliases {
19		spi0 = &espi0;
20	};
21};
22
23&soc {
24	fman@400000 {
25		ethernet@e0000 {
26			phy-handle = <&sgmiiphy21>;
27			phy-connection-type = "sgmii";
28		};
29
30		ethernet@e2000 {
31			phy-handle = <&sgmiiphy22>;
32			phy-connection-type = "sgmii";
33		};
34
35		ethernet@e4000 {
36			phy-handle = <&sgmiiphy23>;
37			phy-connection-type = "sgmii";
38		};
39
40		ethernet@e6000 {
41			phy-handle = <&sgmiiphy24>;
42			phy-connection-type = "sgmii";
43		};
44
45		ethernet@e8000 {
46			status = "disabled";
47		};
48
49		ethernet@ea000 {
50			status = "disabled";
51		};
52
53		ethernet@f0000 {
54			phy-handle = <&xfiphy1>;
55			phy-connection-type = "xgmii";
56		};
57
58		ethernet@f2000 {
59			phy-handle = <&xfiphy2>;
60			phy-connection-type = "xgmii";
61		};
62	};
63
64	fman@500000 {
65		ethernet@e0000 {
66			phy-handle = <&sgmiiphy41>;
67			phy-connection-type = "sgmii";
68		};
69
70		ethernet@e2000 {
71			phy-handle = <&sgmiiphy42>;
72			phy-connection-type = "sgmii";
73		};
74
75		ethernet@e4000 {
76			phy-handle = <&sgmiiphy43>;
77			phy-connection-type = "sgmii";
78		};
79
80		ethernet@e6000 {
81			phy-handle = <&sgmiiphy44>;
82			phy-connection-type = "sgmii";
83		};
84
85		ethernet@e8000 {
86			status = "disabled";
87		};
88
89		ethernet@ea000 {
90			status = "disabled";
91		};
92
93		ethernet@f0000 {
94			phy-handle = <&xfiphy3>;
95			phy-connection-type = "xgmii";
96		};
97
98		ethernet@f2000 {
99			phy-handle = <&xfiphy4>;
100			phy-connection-type = "xgmii";
101		};
102
103		mdio@5fc000 {
104			sgmiiphy21: ethernet-phy@0 {
105				reg = <0x0>;
106			};
107
108			sgmiiphy22: ethernet-phy@1 {
109				reg = <0x1>;
110			};
111
112			sgmiiphy23: ethernet-phy@2 {
113				reg = <0x2>;
114			};
115
116			sgmiiphy24: ethernet-phy@3 {
117				reg = <0x3>;
118			};
119
120			sgmiiphy41: ethernet-phy@4 {
121				reg = <0x4>;
122			};
123
124			sgmiiphy42: ethernet-phy@5 {
125				reg = <0x5>;
126			};
127
128			sgmiiphy43: ethernet-phy@6 {
129				reg = <0x6>;
130			};
131
132			sgmiiphy44: ethernet-phy@7 {
133				reg = <0x7>;
134			};
135		};
136
137		mdio@5fd000 {
138			xfiphy1: ethernet-phy@10 {
139				compatible = "ethernet-phy-id13e5.1002";
140				reg = <0x10>;
141			};
142
143			xfiphy2: ethernet-phy@11 {
144				compatible = "ethernet-phy-id13e5.1002";
145				reg = <0x11>;
146			};
147
148			xfiphy3: ethernet-phy@13 {
149				compatible = "ethernet-phy-id13e5.1002";
150				reg = <0x13>;
151			};
152
153			xfiphy4: ethernet-phy@12 {
154				compatible = "ethernet-phy-id13e5.1002";
155				reg = <0x12>;
156			};
157		};
158	};
159};
160
161&espi0 {
162	status = "okay";
163	flash@0 {
164		compatible = "jedec,spi-nor";
165		#address-cells = <1>;
166		#size-cells = <1>;
167		reg = <0>;
168		spi-max-frequency = <10000000>; /* input clock */
169	};
170};
171
172/include/ "t4240si-post.dtsi"
173