1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_SECURE_BOOT_H 7 #define __FSL_SECURE_BOOT_H 8 #include <asm/config_mpc85xx.h> 9 10 #ifdef CONFIG_NXP_ESBC 11 #if defined(CONFIG_FSL_CORENET) 12 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 13 #elif defined(CONFIG_TARGET_BSC9132QDS) 14 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 15 #elif defined(CONFIG_TARGET_C29XPCIE) 16 #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 17 #else 18 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 19 #endif 20 #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 21 22 #if defined(CONFIG_TARGET_B4860QDS) || \ 23 defined(CONFIG_TARGET_B4420QDS) || \ 24 defined(CONFIG_TARGET_T4240QDS) || \ 25 defined(CONFIG_TARGET_T2080QDS) || \ 26 defined(CONFIG_TARGET_T2080RDB) || \ 27 defined(CONFIG_TARGET_T1042RDB) || \ 28 defined(CONFIG_TARGET_T1042D4RDB) || \ 29 defined(CONFIG_TARGET_T1042RDB_PI) || \ 30 defined(CONFIG_ARCH_T1024) 31 #ifndef CONFIG_SYS_RAMBOOT 32 #define CONFIG_SYS_CPC_REINIT_F 33 #endif 34 #define CONFIG_KEY_REVOCATION 35 #undef CONFIG_SYS_INIT_L3_ADDR 36 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 37 #endif 38 39 #if defined(CONFIG_RAMBOOT_PBL) 40 #undef CONFIG_SYS_INIT_L3_ADDR 41 #ifdef CONFIG_SYS_INIT_L3_VADDR 42 #define CONFIG_SYS_INIT_L3_ADDR \ 43 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 44 0xbff00000 45 #else 46 #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 47 #endif 48 #endif 49 50 #if defined(CONFIG_TARGET_C29XPCIE) 51 #define CONFIG_KEY_REVOCATION 52 #endif 53 54 #if defined(CONFIG_ARCH_P3041) || \ 55 defined(CONFIG_ARCH_P4080) || \ 56 defined(CONFIG_ARCH_P5040) || \ 57 defined(CONFIG_ARCH_P2041) 58 #define CONFIG_FSL_TRUST_ARCH_v1 59 #endif 60 61 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) 62 /* The key used for verification of next level images 63 * is picked up from an Extension Table which has 64 * been verified by the ISBC (Internal Secure boot Code) 65 * in boot ROM of the SoC. 66 * The feature is only applicable in case of NOR boot and is 67 * not applicable in case of RAMBOOT (NAND, SD, SPI). 68 */ 69 #define CONFIG_FSL_ISBC_KEY_EXT 70 #endif 71 #endif /* #ifdef CONFIG_NXP_ESBC */ 72 73 #ifdef CONFIG_CHAIN_OF_TRUST 74 #ifdef CONFIG_SPL_BUILD 75 /* 76 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init 77 * due to space crunch on CPC and thus malloc will not work. 78 */ 79 #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 80 #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 81 #define CONFIG_SPL_JR0_LIODN_S 454 82 #define CONFIG_SPL_JR0_LIODN_NS 458 83 /* 84 * Define the key hash for U-Boot here if public/private key pair used to 85 * sign U-boot are different from the SRK hash put in the fuse 86 * Example of defining KEY_HASH is 87 * #define CONFIG_SPL_UBOOT_KEY_HASH \ 88 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 89 * else leave it defined as NULL 90 */ 91 92 #define CONFIG_SPL_UBOOT_KEY_HASH NULL 93 #endif /* ifdef CONFIG_SPL_BUILD */ 94 95 #define CONFIG_FSL_SEC_MON 96 97 #ifndef CONFIG_SPL_BUILD 98 /* 99 * fsl_setenv_chain_of_trust() must be called from 100 * board_late_init() 101 */ 102 103 /* If Boot Script is not on NOR and is required to be copied on RAM */ 104 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 105 #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 106 #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 107 #define CONFIG_BS_HDR_SIZE 0x00002000 108 #define CONFIG_BS_ADDR_RAM 0x00012000 109 #define CONFIG_BS_ADDR_DEVICE 0x00802000 110 #define CONFIG_BS_SIZE 0x00001000 111 112 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 113 #else 114 115 /* The bootscript header address is different for B4860 because the NOR 116 * mapping is different on B4 due to reduced NOR size. 117 */ 118 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) 119 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 120 #elif defined(CONFIG_FSL_CORENET) 121 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 122 #elif defined(CONFIG_TARGET_BSC9132QDS) 123 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 124 #elif defined(CONFIG_TARGET_C29XPCIE) 125 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 126 #else 127 #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 128 #endif 129 130 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ 131 132 #include <config_fsl_chain_trust.h> 133 #endif /* #ifndef CONFIG_SPL_BUILD */ 134 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 135 #endif 136