1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9
invalidate_icache_all(void)10 void invalidate_icache_all(void)
11 {
12 asm volatile ("fence.i" ::: "memory");
13 }
14
flush_dcache_all(void)15 __weak void flush_dcache_all(void)
16 {
17 }
18
flush_dcache_range(unsigned long start,unsigned long end)19 __weak void flush_dcache_range(unsigned long start, unsigned long end)
20 {
21 }
22
invalidate_icache_range(unsigned long start,unsigned long end)23 void invalidate_icache_range(unsigned long start, unsigned long end)
24 {
25 /*
26 * RISC-V does not have an instruction for invalidating parts of the
27 * instruction cache. Invalidate all of it instead.
28 */
29 invalidate_icache_all();
30 }
31
invalidate_dcache_range(unsigned long start,unsigned long end)32 __weak void invalidate_dcache_range(unsigned long start, unsigned long end)
33 {
34 }
35
cache_flush(void)36 void cache_flush(void)
37 {
38 invalidate_icache_all();
39 flush_dcache_all();
40 }
41
flush_cache(unsigned long addr,unsigned long size)42 void flush_cache(unsigned long addr, unsigned long size)
43 {
44 invalidate_icache_range(addr, addr + size);
45 flush_dcache_range(addr, addr + size);
46 }
47
icache_enable(void)48 __weak void icache_enable(void)
49 {
50 }
51
icache_disable(void)52 __weak void icache_disable(void)
53 {
54 }
55
icache_status(void)56 __weak int icache_status(void)
57 {
58 return 0;
59 }
60
dcache_enable(void)61 __weak void dcache_enable(void)
62 {
63 }
64
dcache_disable(void)65 __weak void dcache_disable(void)
66 {
67 }
68
dcache_status(void)69 __weak int dcache_status(void)
70 {
71 return 0;
72 }
73
enable_caches(void)74 __weak void enable_caches(void)
75 {
76 }
77