1/* SPDX-License-Identifier: GPL-2.0 */ 2/dts-v1/; 3 4#include <dt-bindings/gpio/gpio.h> 5#include <dt-bindings/gpio/x86-gpio.h> 6 7/include/ "skeleton.dtsi" 8/include/ "keyboard.dtsi" 9/include/ "reset.dtsi" 10/include/ "rtc.dtsi" 11 12#include "tsc_timer.dtsi" 13 14#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) 15#include "chromeos-x86.dtsi" 16#include "flashmap-x86-ro.dtsi" 17#include "flashmap-16mb-rw.dtsi" 18#endif 19 20#include <dt-bindings/clock/intel-clock.h> 21#include <dt-bindings/interrupt-controller/irq.h> 22#include <dt-bindings/interrupt-controller/x86-irq.h> 23#include <asm/e820.h> 24#include <asm/intel_pinctrl_defs.h> 25#include <asm/arch-apollolake/cpu.h> 26#include <asm/arch-apollolake/gpe.h> 27#include <asm/arch-apollolake/gpio.h> 28#include <asm/arch-apollolake/iomap.h> 29#include <asm/arch-apollolake/pm.h> 30#include <dt-bindings/clock/intel-clock.h> 31#include <asm/arch-apollolake/fsp/fsp_m_upd.h> 32#include <asm/arch-apollolake/fsp/fsp_s_upd.h> 33#include <dt-bindings/sound/nhlt.h> 34 35/ { 36 model = "Google Coral"; 37 compatible = "google,coral", "intel,apollolake"; 38 39 aliases { 40 cros-ec0 = &cros_ec; 41 fsp = &fsp_s; 42 spi0 = &spi; 43 i2c0 = &i2c_0; 44 i2c1 = &i2c_1; 45 i2c2 = &i2c_2; 46 i2c3 = &i2c_3; 47 i2c4 = &i2c_4; 48 i2c5 = &i2c_5; 49 i2c6 = &i2c_6; 50 i2c7 = &i2c_7; 51 mmc0 = &emmc; 52 mmc1 = &sdmmc; 53 }; 54 55 board: board { 56 compatible = "google,coral"; 57 recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; 58 write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; 59 phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; 60 memconfig-gpios = <&gpio_nw GPIO_101 GPIO_ACTIVE_HIGH 61 &gpio_nw GPIO_102 GPIO_ACTIVE_HIGH 62 &gpio_n GPIO_38 GPIO_ACTIVE_HIGH 63 &gpio_n GPIO_45 GPIO_ACTIVE_HIGH>; 64 65 /* 66 * This is used for reef only: 67 * 68 * skuconfig-gpios = <&gpio_nw GPIO_16 GPIO_ACTIVE_HIGH 69 * &gpio_nw GPIO_17 GPIO_ACTIVE_HIGH>; 70 */ 71 smbios { 72 /* Type 1 table */ 73 system { 74 manufacturer = "Google"; 75 product = "Coral"; 76 version = "rev2"; 77 serial = "123456789"; 78 sku = "sku3"; 79 family = "Google_Coral"; 80 }; 81 82 /* Type 2 table */ 83 baseboard { 84 manufacturer = "Google"; 85 product = "Coral"; 86 asset-tag = "ABC123"; 87 }; 88 89 /* Type 3 table */ 90 chassis { 91 manufacturer = "Google"; 92 }; 93 }; 94 }; 95 96 config { 97 silent_console = <0>; 98 }; 99 100 chosen { 101 stdout-path = &serial; 102 e820-entries = /bits/ 64 < 103 IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED 104 MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>; 105 u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3 106 &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5 107 &sdmmc &maxim_codec &wifi &da_codec &tpm 108 &elan_touchscreen &raydium_touchscreen 109 &elan_touchpad &synaptics_touchpad &wacom_digitizer>; 110 u-boot,acpi-dsdt-order = <&board &lpc>; 111 }; 112 113 clk: clock { 114 compatible = "intel,apl-clk"; 115 #clock-cells = <1>; 116 u-boot,dm-pre-proper; 117 }; 118 119 cpus { 120 u-boot,dm-pre-proper; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 cpu_0: cpu@0 { 125 u-boot,dm-pre-proper; 126 u-boot,dm-spl; 127 device_type = "cpu"; 128 compatible = "intel,apl-cpu"; 129 reg = <0>; 130 intel,apic-id = <0>; 131 }; 132 133 cpu_1: cpu@1 { 134 device_type = "cpu"; 135 compatible = "intel,apl-cpu"; 136 reg = <1>; 137 intel,apic-id = <2>; 138 }; 139 140 cpu_2: cpu@2 { 141 device_type = "cpu"; 142 compatible = "intel,apl-cpu"; 143 reg = <2>; 144 intel,apic-id = <4>; 145 }; 146 147 cpu_3: cpu@3 { 148 device_type = "cpu"; 149 compatible = "intel,apl-cpu"; 150 reg = <3>; 151 intel,apic-id = <6>; 152 }; 153 154 }; 155 156 acpi_gpe: general-purpose-events { 157 u-boot,dm-pre-proper; 158 reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; 159 compatible = "intel,acpi-gpe"; 160 interrupt-controller; 161 #interrupt-cells = <2>; 162 }; 163 164 coreboot-video { 165 /* This will only activate when booted from coreboot */ 166 compatible = "coreboot-fb"; 167 }; 168 169 keyboard { 170 intel,duplicate-por; 171 }; 172 173 pci { 174 compatible = "pci-x86"; 175 #address-cells = <3>; 176 #size-cells = <2>; 177 u-boot,dm-pre-reloc; 178 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 179 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 180 0x01000000 0x0 0x1000 0x1000 0 0xefff>; 181 u-boot,skip-auto-config-until-reloc; 182 183 host_bridge: host-bridge@0,0 { 184 u-boot,dm-pre-reloc; 185 reg = <0x00000000 0 0 0 0>; 186 compatible = "intel,apl-hostbridge"; 187 pciex-region-size = <0x10000000>; 188 fspm,training-delay = <21>; 189 /* 190 * Parameters used by the FSP-S binary blob. This is 191 * really unfortunate since these parameters mostly 192 * relate to drivers but we need them in one place. We 193 * could put them in the driver nodes easily, but then 194 * would have to scan each node to find them. So just 195 * dump them here for now. 196 */ 197 fsp_s: fsp-s { 198 }; 199 fsp_m: fsp-m { 200 u-boot,dm-spl; 201 }; 202 203 nhlt { 204 intel,dmic-channels = <4>; 205 }; 206 }; 207 208 punit@0,1 { 209 u-boot,dm-pre-proper; 210 u-boot,dm-spl; 211 reg = <0x00000800 0 0 0 0>; 212 compatible = "intel,apl-punit"; 213 }; 214 215 gma@2,0 { 216 u-boot,dm-pre-proper; 217 reg = <0x00001000 0 0 0 0>; 218 compatible = "fsp-fb"; 219 }; 220 221 p2sb: p2sb@d,0 { 222 u-boot,dm-pre-reloc; 223 reg = <0x02006810 0 0 0 0>; 224 compatible = "intel,p2sb"; 225 early-regs = <IOMAP_P2SB_BAR 0x100000>; 226 pci,no-autoconfig; 227 228 n { 229 compatible = "intel,apl-pinctrl"; 230 u-boot,dm-pre-reloc; 231 intel,p2sb-port-id = <PID_GPIO_N>; 232 acpi,path = "\\_SB.GPO0"; 233 gpio_n: gpio-n { 234 compatible = "intel,gpio"; 235 u-boot,dm-pre-reloc; 236 gpio-controller; 237 #gpio-cells = <2>; 238 linux-name = "INT3452:00"; 239 }; 240 }; 241 242 nw { 243 u-boot,dm-pre-reloc; 244 compatible = "intel,apl-pinctrl"; 245 intel,p2sb-port-id = <PID_GPIO_NW>; 246 #gpio-cells = <2>; 247 acpi,path = "\\_SB.GPO1"; 248 gpio_nw: gpio-nw { 249 compatible = "intel,gpio"; 250 u-boot,dm-pre-reloc; 251 gpio-controller; 252 #gpio-cells = <2>; 253 linux-name = "INT3452:01"; 254 }; 255 }; 256 257 w { 258 u-boot,dm-pre-reloc; 259 compatible = "intel,apl-pinctrl"; 260 intel,p2sb-port-id = <PID_GPIO_W>; 261 #gpio-cells = <2>; 262 acpi,path = "\\_SB.GPO2"; 263 gpio_w: gpio-w { 264 compatible = "intel,gpio"; 265 u-boot,dm-pre-reloc; 266 gpio-controller; 267 #gpio-cells = <2>; 268 linux-name = "INT3452:02"; 269 }; 270 }; 271 272 sw { 273 u-boot,dm-pre-reloc; 274 compatible = "intel,apl-pinctrl"; 275 intel,p2sb-port-id = <PID_GPIO_SW>; 276 #gpio-cells = <2>; 277 acpi,path = "\\_SB.GPO3"; 278 gpio_sw: gpio-sw { 279 compatible = "intel,gpio"; 280 u-boot,dm-pre-reloc; 281 gpio-controller; 282 #gpio-cells = <2>; 283 linux-name = "INT3452:03"; 284 }; 285 }; 286 287 itss { 288 u-boot,dm-pre-reloc; 289 compatible = "intel,itss"; 290 intel,p2sb-port-id = <PID_ITSS>; 291 intel,pmc-routes = < 292 PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 293 PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32 294 PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0 295 PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32 296 PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64 297 PMC_GPE_N_31_0 GPIO_GPE_N_31_0 298 PMC_GPE_N_63_32 GPIO_GPE_N_63_32 299 PMC_GPE_W_31_0 GPIO_GPE_W_31_0>; 300 }; 301 }; 302 303 pmc@d,1 { 304 u-boot,dm-pre-reloc; 305 reg = <0x6900 0 0 0 0>; 306 307 /* 308 * Values for BAR0, BAR2 and ACPI_BASE for when PCI 309 * auto-configure is not available 310 */ 311 early-regs = <0xfe042000 0x2000 312 0xfe044000 0x2000 313 IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; 314 compatible = "intel,apl-pmc"; 315 gpe0-dwx-mask = <0xf>; 316 gpe0-dwx-shift-base = <4>; 317 318 /* 319 * GPE configuration 320 * Note that GPE events called out in ASL code rely on 321 * this route, i.e., if this route changes then the 322 * affected GPE * offset bits also need to be changed. 323 * This sets the PMC register GPE_CFG fields. 324 */ 325 gpe0-dw = <PMC_GPE_N_31_0 326 PMC_GPE_N_63_32 327 PMC_GPE_SW_31_0>; 328 gpe0-sts = <0x20>; 329 gpe0-en = <0x30>; 330 }; 331 332 audio@e,0 { 333 reg = <0x7000 0 0 0 0>; 334 compatible = "simple-bus"; 335 acpi,name = "HDAS"; 336 i2s { 337 compatible = "fred"; 338 }; 339 maxim_codec: maxim-codec { 340 compatible = "maxim,max98357a"; 341 acpi,ddn = "Maxim Integrated 98357A Amplifier"; 342 sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>; 343 sdmode-delay = <5>; 344 acpi,name = "MAXM"; 345 acpi,hid = "MX98357A"; 346 acpi,audio-link = <AUDIO_LINK_SSP5>; 347 }; 348 }; 349 350 spi: fast-spi@d,2 { 351 u-boot,dm-pre-proper; 352 u-boot,dm-spl; 353 reg = <0x02006a10 0 0 0 0>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "intel,fast-spi"; 357 early-regs = <IOMAP_SPI_BASE 0x1000>; 358 intel,hardware-seq = <1>; 359 360 fwstore_spi: spi-flash@0 { 361 #size-cells = <1>; 362 #address-cells = <1>; 363 u-boot,dm-pre-proper; 364 u-boot,dm-spl; 365 reg = <0>; 366 m25p,fast-read; 367 compatible = "winbond,w25q128fw", 368 "jedec,spi-nor"; 369 rw-mrc-cache { 370 label = "rw-mrc-cache"; 371 reg = <0x008e0000 0x00010000>; 372 u-boot,dm-pre-reloc; 373 }; 374 rw-var-mrc-cache { 375 label = "rw-mrc-cache"; 376 reg = <0x008f0000 0x0001000>; 377 u-boot,dm-pre-reloc; 378 }; 379 }; 380 }; 381 382 /* WiFi */ 383 pcie-a0@14,0 { 384 reg = <0x0000a000 0 0 0 0>; 385 acpi,name = "RP01"; 386 wifi: wifi { 387 compatible = "intel,generic-wifi"; 388 acpi,ddn = "Intel WiFi"; 389 acpi,name = "WF00"; 390 acpi,wake = <GPE0_DW3_00>; 391 interrupts-extended = <&acpi_gpe 0x3c 0>; 392 }; 393 }; 394 395 i2c_0: i2c2@16,0 { 396 compatible = "intel,apl-i2c"; 397 reg = <0x0200b010 0 0 0 0>; 398 clocks = <&clk CLK_I2C>; 399 i2c-scl-rising-time-ns = <104>; 400 i2c-scl-falling-time-ns = <52>; 401 clock-frequency = <400000>; 402 i2c,speeds = <100000 400000 1000000>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 da_codec: da-codec { 406 reg = <0x1a>; 407 compatible = "dlg,da7219"; 408 interrupts-extended = <&acpi_gpe GPIO_116_IRQ 409 (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; 410 acpi,name = "DLG7"; 411 acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec"; 412 acpi,audio-link = <AUDIO_LINK_SSP1>; 413 dlg,micbias-lvl = <2600>; 414 dlg,mic-amp-in-sel = "diff"; 415 da7219_aad { 416 dlg,btn-cfg = <50>; 417 dlg,mic-det-thr = <500>; 418 dlg,jack-ins-deb = <20>; 419 dlg,jack-det-rate = "32ms_64ms"; 420 dlg,jack-rem-deb = <1>; 421 dlg,a-d-btn-thr = <0xa>; 422 dlg,d-b-btn-thr = <0x16>; 423 dlg,b-c-btn-thr = <0x21>; 424 dlg,c-mic-btn-thr = <0x3e>; 425 dlg,btn-avg = <4>; 426 dlg,adc-1bit-rpt = <1>; 427 }; 428 }; 429 }; 430 431 i2c_1: i2c2@16,1 { 432 compatible = "intel,apl-i2c"; 433 reg = <0x0200b110 0 0 0 0>; 434 clocks = <&clk CLK_I2C>; 435 clock-frequency = <400000>; 436 i2c,speeds = <100000 400000 1000000 3400000>; 437 i2c-scl-rising-time-ns = <52>; 438 i2c-scl-falling-time-ns = <52>; 439 }; 440 441 i2c_2: i2c2@16,2 { 442 compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; 443 reg = <0x0200b210 0 0 0 0>; 444 early-regs = <IOMAP_I2C2_BASE 0x1000>; 445 u-boot,dm-pre-proper; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 clock-frequency = <400000>; 449 i2c,speeds = <100000 400000 1000000>; 450 clocks = <&clk CLK_I2C>; 451 i2c-scl-rising-time-ns = <57>; 452 i2c-scl-falling-time-ns = <28>; 453 tpm: tpm@50 { 454 reg = <0x50>; 455 compatible = "google,cr50"; 456 u-boot,dm-pre-proper; 457 u-boot,i2c-offset-len = <0>; 458 ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; 459 interrupts-extended = <&acpi_gpe GPIO_28_IRQ 460 IRQ_TYPE_EDGE_FALLING>; 461 acpi,hid = "GOOG0005"; 462 acpi,ddn = "I2C TPM"; 463 acpi,name = "TPMI"; 464 }; 465 }; 466 467 i2c_3: i2c2@16,3 { 468 compatible = "intel,apl-i2c"; 469 reg = <0x0200b310 0 0 0 0>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&clk CLK_I2C>; 473 i2c-scl-rising-time-ns = <76>; 474 i2c-scl-falling-time-ns = <164>; 475 clock-frequency = <400000>; 476 i2c,speeds = <100000 400000>; 477 elan_touchscreen: elan-touchscreen@10 { 478 compatible = "i2c-chip"; 479 reg = <0x10>; 480 acpi,hid = "ELAN0001"; 481 acpi,ddn = "ELAN Touchscreen"; 482 interrupts-extended = <&acpi_gpe GPIO_21_IRQ 483 IRQ_TYPE_EDGE_FALLING>; 484 linux,probed; 485 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; 486 reset-delay-ms = <20>; 487 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; 488 enable-delay-ms = <1>; 489 acpi,has-power-resource; 490 }; 491 492 raydium_touchscreen: raydium-touchscreen@39 { 493 compatible = "i2c-chip"; 494 reg = <0x39>; 495 acpi,hid = "RAYD0001"; 496 acpi,ddn = "Raydium Touchscreen"; 497 interrupts-extended = <&acpi_gpe GPIO_21_IRQ 498 IRQ_TYPE_EDGE_FALLING>; 499 linux,probed; 500 reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; 501 reset-delay-ms = <1>; 502 enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; 503 enable-delay-ms = <50>; 504 acpi,has-power-resource; 505 }; 506 }; 507 508 i2c_4: i2c2@17,0 { 509 compatible = "intel,apl-i2c"; 510 reg = <0x0200b810 0 0 0 0>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&clk CLK_I2C>; 514 i2c-sda-hold-time-ns = <350>; 515 i2c-scl-rising-time-ns = <114>; 516 i2c-scl-falling-time-ns = <164>; 517 clock-frequency = <400000>; 518 i2c,speeds = <100000 400000>; 519 elan_touchpad: elan-touchpad@15 { 520 compatible = "i2c-chip"; 521 reg = <0x15>; 522 u-boot,i2c-offset-len = <0>; 523 acpi,hid = "ELAN0000"; 524 acpi,ddn = "ELAN Touchpad"; 525 interrupts-extended = <&acpi_gpe GPIO_18_IRQ 526 IRQ_TYPE_EDGE_FALLING>; 527 acpi,wake = <GPE0_DW1_15>; 528 linux,probed; 529 }; 530 synaptics_touchpad: synaptics-touchpad@2c { 531 compatible = "hid-over-i2c"; 532 reg = <0x2c>; 533 acpi,hid = "PNP0C50"; 534 acpi,ddn = "Synaptics Touchpad"; 535 interrupts-extended = <&acpi_gpe GPIO_18_IRQ 536 IRQ_TYPE_EDGE_FALLING>; 537 acpi,wake = <GPE0_DW1_15>; 538 linux,probed; 539 hid-descr-addr = <0x20>; 540 }; 541 }; 542 543 i2c_5: i2c2@17,1 { 544 compatible = "intel,apl-i2c"; 545 reg = <0x0200b910 0 0 0 0>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clocks = <&clk CLK_I2C>; 549 i2c-scl-rising-time-ns = <76>; 550 i2c-scl-falling-time-ns = <164>; 551 clock-frequency = <400000>; 552 i2c,speeds = <100000 400000 1000000>; 553 wacom_digitizer: wacom-digitizer@9 { 554 compatible = "hid-over-i2c"; 555 reg = <0x9>; 556 acpi,hid = "WCOM50C1"; 557 acpi,ddn = "WCOM Digitizer"; 558 interrupts-extended = <&acpi_gpe GPIO_13_IRQ 559 (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; 560 hid-descr-addr = <0x1>; 561 }; 562 }; 563 564 i2c_6: i2c2@17,2 { 565 compatible = "intel,apl-i2c"; 566 reg = <0x0200ba10 0 0 0 0>; 567 clocks = <&clk CLK_I2C>; 568 status = "disabled"; 569 }; 570 571 i2c_7: i2c2@17,3 { 572 compatible = "intel,apl-i2c"; 573 reg = <0x0200bb10 0 0 0 0>; 574 clocks = <&clk CLK_I2C>; 575 status = "disabled"; 576 }; 577 578 serial: serial@18,2 { 579 reg = <0x0200c210 0 0 0 0>; 580 u-boot,dm-pre-reloc; 581 compatible = "intel,apl-ns16550"; 582 early-regs = <0xde000000 0x20>; 583 reg-shift = <2>; 584 clock-frequency = <1843200>; 585 current-speed = <115200>; 586 acpi,name = "URT3"; 587 pci,no-autoconfig; 588 }; 589 590 sdmmc: sdmmc@1b,0 { 591 reg = <0x0000d800 0 0 0 0>; 592 compatible = "intel,apl-sd"; 593 cd-gpios = <&gpio_sw GPIO_177 GPIO_ACTIVE_LOW>; 594 acpi,name = "SDCD"; 595 }; 596 597 emmc: emmc@1c,0 { 598 reg = <0x0000e000 0 0 0 0>; 599 compatible = "intel,apl-emmc"; 600 non-removable; 601 }; 602 603 pch: pch@1f,0 { 604 reg = <0x0000f800 0 0 0 0>; 605 compatible = "intel,apl-pch"; 606 u-boot,dm-pre-reloc; 607 #address-cells = <1>; 608 #size-cells = <1>; 609 610 lpc: lpc { 611 compatible = "intel,apl-lpc"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 u-boot,dm-pre-reloc; 615 cros_ec: cros-ec { 616 u-boot,dm-pre-proper; 617 u-boot,dm-vpl; 618 compatible = "google,cros-ec-lpc"; 619 reg = <0x204 1 0x200 1 0x880 0x80>; 620 621 /* 622 * Describes the flash memory within 623 * the EC 624 */ 625 #address-cells = <1>; 626 #size-cells = <1>; 627 flash@8000000 { 628 reg = <0x08000000 0x20000>; 629 erase-value = <0xff>; 630 }; 631 }; 632 }; 633 }; 634 }; 635 636}; 637 638&host_bridge { 639 /* 640 * PL1 override 12000 mW: the energy calculation is wrong with the 641 * current VR solution. Experiments show that SoC TDP max (6W) can be 642 * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W. 643 */ 644 tdp-pl-override-mw = <12000 15000>; 645 646 early-pads = < 647 /* These two are for the debug UART */ 648 GPIO_46 /* UART2 RX */ 649 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 650 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 651 652 GPIO_47 /* UART2 TX */ 653 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 654 (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 655 656 GPIO_75 /* I2S1_BCLK -- PCH_WP */ 657 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP) 658 (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE) 659 660 /* I2C2 - TPM */ 661 GPIO_128 /* LPSS_I2C2_SDA */ 662 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 663 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 664 GPIO_129 /* LPSS_I2C2_SCL */ 665 (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) 666 (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 667 GPIO_28 /* TPM IRQ */ 668 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | 669 PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | 670 PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) 671 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) 672 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ 673 674 /* 675 * WLAN_PE_RST - default to deasserted just in case FSP 676 * misbehaves 677 */ 678 GPIO_122 /* SIO_SPI_2_RXD */ 679 (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | 680 PAD_CFG0_RX_DISABLE | 0) 681 (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) 682 683 /* LPC */ 684 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ 685 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ 686 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) 687 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ 688 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ 689 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ 690 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ 691 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ 692 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ 693 694 PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ 695 PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ 696 PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ 697 PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ 698 >; 699}; 700 701&fsp_m { 702 fspm,package = <PACKAGE_BGA>; 703 fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; 704 fspm,memory-down = <MEMORY_DOWN_YES>; 705 fspm,scrambler-support = <1>; 706 fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>; 707 fspm,channel-hash-mask = <0x36>; 708 fspm,slice-hash-mask = <0x9>; 709 fspm,dual-rank-support-enable = <1>; 710 fspm,low-memory-max-value = <2048>; 711 fspm,ch0-rank-enable = <1>; 712 fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; 713 fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; 714 fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | 715 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 716 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 717 fspm,ch1-rank-enable = <1>; 718 fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; 719 fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; 720 fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | 721 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 722 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 723 fspm,ch2-rank-enable = <1>; 724 fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; 725 fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; 726 fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | 727 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 728 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 729 fspm,ch3-rank-enable = <1>; 730 fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; 731 fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; 732 fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | 733 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; 734 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; 735 fspm,fspm,skip-cse-rbp = <1>; 736 737 fspm,ch-bit-swizzling = /bits/ 8 < 738 /* LP4_PHYS_CH0A */ 739 740 /* DQA[0:7] pins of LPDDR4 module */ 741 6 7 5 4 3 1 0 2 742 /* DQA[8:15] pins of LPDDR4 module */ 743 12 10 11 13 14 8 9 15 744 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 745 16 22 23 20 18 17 19 21 746 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 747 30 28 29 25 24 26 27 31 748 749 /* LP4_PHYS_CH0B */ 750 /* DQA[0:7] pins of LPDDR4 module */ 751 7 3 5 2 6 0 1 4 752 /* DQA[8:15] pins of LPDDR4 module */ 753 9 14 12 13 10 11 8 15 754 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 755 20 22 23 16 19 17 18 21 756 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 757 28 24 26 27 29 30 31 25 758 759 /* LP4_PHYS_CH1A */ 760 761 /* DQA[0:7] pins of LPDDR4 module */ 762 2 1 6 7 5 4 3 0 763 /* DQA[8:15] pins of LPDDR4 module */ 764 11 10 8 9 12 15 13 14 765 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 766 17 23 19 16 21 22 20 18 767 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 768 31 29 26 25 28 27 24 30 769 770 /* LP4_PHYS_CH1B */ 771 772 /* DQA[0:7] pins of LPDDR4 module */ 773 4 3 7 5 6 1 0 2 774 /* DQA[8:15] pins of LPDDR4 module */ 775 15 9 8 11 14 13 12 10 776 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 777 20 23 22 21 18 19 16 17 778 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 779 25 28 30 31 26 27 24 29>; 780 781 fspm,dimm0-spd-address = <0>; 782 fspm,dimm1-spd-address = <0>; 783 fspm,skip-cse-rbp = <1>; 784 fspm,enable-s3-heci2 = <0>; 785}; 786 787&fsp_s { 788 u-boot,dm-pre-proper; 789 790 fsps,ish-enable = <0>; 791 fsps,enable-sata = <0>; 792 fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>; 793 fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>; 794 fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>; 795 fsps,spi1-enable = <SPIX_ENABLE_DISABLED>; 796 fsps,spi2-enable = <SPIX_ENABLE_DISABLED>; 797 fsps,sdio-enabled = <0>; 798 799 /* Disable unused clkreq of PCIe root ports */ 800 fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */ 801 CLKREQ_DISABLED 802 CLKREQ_DISABLED 803 CLKREQ_DISABLED 804 CLKREQ_DISABLED 805 CLKREQ_DISABLED>; 806 807 /* 808 * GPIO for PERST_0 809 * If the Board has PERST_0 signal, assign the GPIO 810 * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF 811 * 812 * This are not used yet, so comment them out for now. 813 * 814 * prt0-gpio = <GPIO_122>; 815 * 816 * GPIO for SD card detect 817 * sdcard-cd-gpio = <GPIO_177>; 818 */ 819 820 /* 821 * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2, 822 * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2 823 * 824 * EMMC TX DATA Delay 1 825 * Refer to EDS-Vol2-22.3 826 * [14:8] steps of delay for HS400, each 125ps 827 * [6:0] steps of delay for SDR104/HS200, each 125ps 828 */ 829 830 /* 831 * EMMC TX DATA Delay 2 832 * Refer to EDS-Vol2-22.3. 833 * [30:24] steps of delay for SDR50, each 125ps 834 * [22:16] steps of delay for DDR50, each 125ps 835 * [14:8] steps of delay for SDR25/HS50, each 125ps 836 * [6:0] steps of delay for SDR12, each 125ps 837 */ 838 839 /* 840 * EMMC RX CMD/DATA Delay 1 841 * Refer to EDS-Vol2-22.3. 842 * [30:24] steps of delay for SDR50, each 125ps 843 * [22:16] steps of delay for DDR50, each 125ps 844 * [14:8] steps of delay for SDR25/HS50, each 125ps 845 * [6:0] steps of delay for SDR12, each 125ps 846 */ 847 848 /* 849 * EMMC RX CMD/DATA Delay 2 850 * Refer to EDS-Vol2-22.3. 851 * [17:16] stands for Rx Clock before Output Buffer 852 * [14:8] steps of delay for Auto Tuning Mode, each 125ps 853 * [6:0] steps of delay for HS200, each 125ps 854 */ 855 /* Enable DPTF */ 856 fsps,dptf-enabled; 857 fsps,emmc-tx-data-cntl1 = <0x0c16>; 858 fsps,emmc-tx-data-cntl2 = <0x28162828>; 859 fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; 860 fsps,emmc-rx-cmd-data-cntl2 = <0x10008>; 861 862 /* Enable Audio Clock and Power gating */ 863 fsps,hd-audio-clk-gate = <1>; 864 fsps,hd-audio-pwr-gate = <1>; 865 fsps,bios-cfg-lock-down = <1>; 866 867 /* Enable WiFi */ 868 fsps,pcie-root-port-en = [01 00 00 00 00 00]; 869 fsps,pcie-rp-hot-plug = [00 00 00 00 00 00]; 870 871 fsps,skip-mp-init = <1>; 872 fsps,spi-eiss = <0>; 873 fsps,rtc-lock = <0>; 874 875 fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01]; 876 fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03]; 877 878 fsps,lpss-s0ix-enable = <1>; 879 fsps,usb-otg = <0>; 880 fsps,monitor-mwait-enable = <0>; 881 882 /* 883 * TODO(sjg@chromium.org): Move this to the I2C nodes 884 * Intel Common SoC Config 885 *+-------------------+---------------------------+ 886 *| Field | Value | 887 *+-------------------+---------------------------+ 888 *| I2C0 | Audio | 889 *| I2C2 | TPM | 890 *| I2C3 | Touchscreen | 891 *| I2C4 | Trackpad | 892 *| I2C5 | Digitizer | 893 *+-------------------+---------------------------+ 894 * 895 common_soc_config" = "{ 896 .i2c[0] = { 897 .speed = I2C_SPEED_FAST, 898 .rise-time-ns = 104, 899 .fall-time-ns = 52, 900 }, 901 .i2c[2] = { 902 .early_init = 1, 903 .speed = I2C_SPEED_FAST, 904 .rise-time-ns = 57, 905 .fall-time-ns = 28, 906 }, 907 .i2c[3] = { 908 .speed = I2C_SPEED_FAST, 909 .rise-time-ns = 76, 910 .fall-time-ns = 164, 911 }, 912 .i2c[4] = { 913 .speed = I2C_SPEED_FAST, 914 .rise-time-ns = 114, 915 .fall-time-ns = 164, 916 .data_hold_time_ns = 350, 917 }, 918 .i2c[5] = { 919 .speed = I2C_SPEED_FAST, 920 .rise-time-ns = 152, 921 .fall-time-ns = 30, 922 }, 923 }" 924 */ 925 926 /* Minimum SLP S3 assertion width 28ms */ 927 slp-s3-assertion-width-usecs = <28000>; 928 929 pads = < 930 /* PCIE_WAKE[0:3]_N */ 931 PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */ 932 PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */ 933 PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */ 934 PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */ 935 936 /* EMMC interface */ 937 PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */ 938 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */ 939 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */ 940 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */ 941 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */ 942 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */ 943 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */ 944 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */ 945 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */ 946 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */ 947 PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */ 948 949 /* SDIO -- unused */ 950 PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */ 951 PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */ 952 /* Configure SDIO to enable power gating */ 953 PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */ 954 PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */ 955 PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */ 956 PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */ 957 958 /* SDCARD */ 959 /* Pull down clock by 20K */ 960 PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */ 961 PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */ 962 PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */ 963 PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */ 964 PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */ 965 /* Card detect is active LOW with external pull up */ 966 PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */ 967 PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */ 968 /* CLK feedback, internal signal, needs 20K pull down */ 969 PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */ 970 /* No h/w write proect for uSD cards, pull down by 20K */ 971 PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */ 972 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */ 973 PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */ 974 975 /* SMBus -- unused */ 976 PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */ 977 PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */ 978 PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */ 979 980 /* LPC */ 981 PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ 982 PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ 983 PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) 984 PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ 985 PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ 986 PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ 987 PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ 988 PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ 989 PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ 990 991 /* I2C0 - Audio */ 992 PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */ 993 PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */ 994 995 /* I2C1 - NFC with external pulls */ 996 PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */ 997 PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */ 998 999 /* I2C2 - TPM */ 1000 PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */ 1001 PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */ 1002 1003 /* I2C3 - touch */ 1004 PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */ 1005 PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */ 1006 1007 /* I2C4 - trackpad */ 1008 /* LPSS_I2C4_SDA */ 1009 PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1) 1010 /* LPSS_I2C4_SCL */ 1011 PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1) 1012 1013 /* I2C5 -- pen with external pulls */ 1014 PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */ 1015 PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */ 1016 1017 /* I2C6-7 -- unused */ 1018 PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */ 1019 PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */ 1020 PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */ 1021 PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */ 1022 1023 /* Audio Amp - I2S6 */ 1024 PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */ 1025 PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */ 1026 PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */ 1027 PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */ 1028 1029 /* NFC Reset */ 1030 PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */ 1031 1032 PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */ 1033 1034 /* Touch enable */ 1035 PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */ 1036 1037 PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */ 1038 PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */ 1039 PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */ 1040 1041 /* PCIE_CLKREQ[0:3]_N */ 1042 PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */ 1043 PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */ 1044 PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */ 1045 PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */ 1046 1047 /* OSC_CLK_OUT_[0:4] -- unused */ 1048 PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP) 1049 PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP) 1050 PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP) 1051 PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP) 1052 PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP) 1053 1054 /* PMU Signals */ 1055 PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */ 1056 PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */ 1057 PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */ 1058 PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */ 1059 PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */ 1060 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */ 1061 PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */ 1062 PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */ 1063 PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */ 1064 PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */ 1065 PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */ 1066 PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */ 1067 1068 /* DDI[0:1] SDA and SCL -- unused */ 1069 PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */ 1070 PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */ 1071 PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */ 1072 PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */ 1073 1074 /* MIPI I2C -- unused */ 1075 PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */ 1076 PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */ 1077 1078 /* Panel 0 control */ 1079 PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */ 1080 PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */ 1081 PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */ 1082 1083 /* Panel 1 control -- unused */ 1084 PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */ 1085 PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */ 1086 PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */ 1087 1088 /* Hot plug detect */ 1089 PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */ 1090 PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */ 1091 1092 /* MDSI signals -- unused */ 1093 PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */ 1094 PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */ 1095 1096 /* USB overcurrent pins */ 1097 PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */ 1098 PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */ 1099 1100 /* PMC SPI -- almost entirely unused */ 1101 PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP) 1102 PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */ 1103 PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP) 1104 PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP) 1105 PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP) 1106 PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP) 1107 1108 /* PMIC Signals Unused signals related to an old PMIC interface */ 1109 PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */ 1110 PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */ 1111 PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */ 1112 PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */ 1113 PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */ 1114 PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */ 1115 PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */ 1116 PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */ 1117 PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */ 1118 1119 /* I2S1 -- largely unused */ 1120 PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */ 1121 PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */ 1122 PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */ 1123 PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */ 1124 PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */ 1125 1126 /* DMIC or I2S4 */ 1127 /* AVS_DMIC_CLK_A1 */ 1128 PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE) 1129 PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */ 1130 PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */ 1131 PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */ 1132 PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */ 1133 1134 /* I2S2 -- Headset amp */ 1135 PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */ 1136 PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */ 1137 PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */ 1138 PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */ 1139 PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */ 1140 1141 /* I2S3 -- largely unused */ 1142 PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */ 1143 PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */ 1144 PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */ 1145 PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */ 1146 1147 /* Fast SPI */ 1148 PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */ 1149 PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */ 1150 PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */ 1151 PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */ 1152 PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ 1153 PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ 1154 PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */ 1155 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */ 1156 PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */ 1157 1158 /* SIO_SPI_0 - Used for FP */ 1159 PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */ 1160 PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */ 1161 PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */ 1162 PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */ 1163 1164 /* SIO_SPI_1 -- largely unused */ 1165 PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */ 1166 PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */ 1167 PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */ 1168 /* Headset interrupt */ 1169 PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */ 1170 PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */ 1171 1172 /* SIO_SPI_2 -- unused */ 1173 PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */ 1174 PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */ 1175 PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */ 1176 PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */ 1177 /* WLAN_PE_RST - default to deasserted */ 1178 PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */ 1179 PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */ 1180 1181 /* Debug tracing */ 1182 PAD_CFG_GPI(GPIO_0, UP_20K, DEEP) 1183 PAD_CFG_GPI(GPIO_1, UP_20K, DEEP) 1184 PAD_CFG_GPI(GPIO_2, UP_20K, DEEP) 1185 PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */ 1186 PAD_CFG_GPI(GPIO_4, UP_20K, DEEP) 1187 PAD_CFG_GPI(GPIO_5, UP_20K, DEEP) 1188 PAD_CFG_GPI(GPIO_6, UP_20K, DEEP) 1189 PAD_CFG_GPI(GPIO_7, UP_20K, DEEP) 1190 PAD_CFG_GPI(GPIO_8, UP_20K, DEEP) 1191 1192 PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */ 1193 PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */ 1194 PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */ 1195 PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */ 1196 PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */ 1197 PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */ 1198 PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */ 1199 PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */ 1200 PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */ 1201 PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */ 1202 PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */ 1203 PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */ 1204 PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */ 1205 PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */ 1206 PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */ 1207 PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */ 1208 PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ 1209 PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */ 1210 PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */ 1211 PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */ 1212 PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */ 1213 PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */ 1214 PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */ 1215 PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */ 1216 PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */ 1217 PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */ 1218 PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */ 1219 PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */ 1220 PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */ 1221 1222 /* LPSS_UART[0:2] */ 1223 PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ 1224 /* Next 2 are straps */ 1225 PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */ 1226 PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */ 1227 PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */ 1228 PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */ 1229 PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */ 1230 PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */ 1231 PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ 1232 PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */ 1233 PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */ 1234 PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */ 1235 PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */ 1236 1237 /* Camera interface -- completely unused */ 1238 PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */ 1239 PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */ 1240 PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */ 1241 PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */ 1242 PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */ 1243 PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */ 1244 PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */ 1245 PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */ 1246 PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */ 1247 PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */ 1248 PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */ 1249 PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ 1250 >; 1251}; 1252 1253&rtc { 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 u-boot,dm-pre-proper; 1257}; 1258