1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  */
5 
6 #ifndef __X86_CACHE_H__
7 #define __X86_CACHE_H__
8 
9 /*
10  * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
11  */
12 #define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE
13 
wbinvd(void)14 static inline void wbinvd(void)
15 {
16 	asm volatile ("wbinvd" : : : "memory");
17 }
18 
invd(void)19 static inline void invd(void)
20 {
21 	asm volatile("invd" : : : "memory");
22 }
23 
24 /* Enable caches and write buffer */
25 void enable_caches(void);
26 
27 /* Disable caches and write buffer */
28 void disable_caches(void);
29 
30 #endif /* __X86_CACHE_H__ */
31