1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <init.h>
11 #include <log.h>
12 #include <rtc.h>
13 #include <acpi/acpi_s3.h>
14 #include <asm/cmos_layout.h>
15 #include <asm/early_cmos.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/mrccache.h>
19 #include <asm/post.h>
20 #include <asm/processor.h>
21 #include <asm/fsp/fsp_support.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
checkcpu(void)25 int checkcpu(void)
26 {
27 return 0;
28 }
29
print_cpuinfo(void)30 int print_cpuinfo(void)
31 {
32 post_code(POST_CPU_INFO);
33 return default_print_cpuinfo();
34 }
35
fsp_init_phase_pci(void)36 int fsp_init_phase_pci(void)
37 {
38 u32 status;
39
40 /* call into FspNotify */
41 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
42 status = fsp_notify(NULL, INIT_PHASE_PCI);
43 if (status)
44 debug("fail, error code %x\n", status);
45 else
46 debug("OK\n");
47
48 return status ? -EPERM : 0;
49 }
50
board_final_init(void)51 void board_final_init(void)
52 {
53 u32 status;
54
55 /* call into FspNotify */
56 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
57 status = fsp_notify(NULL, INIT_PHASE_BOOT);
58 if (status)
59 debug("fail, error code %x\n", status);
60 else
61 debug("OK\n");
62 }
63
fsp_save_s3_stack(void)64 int fsp_save_s3_stack(void)
65 {
66 struct udevice *dev;
67 int ret;
68
69 if (gd->arch.prev_sleep_state == ACPI_S3)
70 return 0;
71
72 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
73 if (ret) {
74 debug("Cannot find RTC: err=%d\n", ret);
75 return -ENODEV;
76 }
77
78 /* Save the stack address to CMOS */
79 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
80 if (ret) {
81 debug("Save stack address to CMOS: err=%d\n", ret);
82 return -EIO;
83 }
84
85 return 0;
86 }
87