1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Xtensa processor core configuration information. 4 * This file is autogenerated, please do not edit. 5 * 6 * Copyright (C) 1999-2010 Tensilica Inc. 7 */ 8 9 #ifndef _XTENSA_CORE_CONFIGURATION_H 10 #define _XTENSA_CORE_CONFIGURATION_H 11 12 13 /**************************************************************************** 14 Parameters Useful for Any Code, USER or PRIVILEGED 15 ****************************************************************************/ 16 17 /* 18 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 19 * configured, and a value of 0 otherwise. These macros are always defined. 20 */ 21 22 23 /*---------------------------------------------------------------------- 24 ISA 25 ----------------------------------------------------------------------*/ 26 27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 28 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 29 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 30 #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 31 #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 32 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 35 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 36 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 37 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 38 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 39 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 40 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 41 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 42 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 43 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 44 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 45 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 46 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 47 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 48 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 49 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 50 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 51 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 52 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 53 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 54 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 55 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 56 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 57 #define XCHAL_NUM_CONTEXTS 1 /* */ 58 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 59 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 60 #define XCHAL_HAVE_PRID 1 /* processor ID register */ 61 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 62 #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 63 #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 64 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 65 #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 66 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 67 #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 68 #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 69 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 70 #define XCHAL_HAVE_FP 0 /* floating point pkg */ 71 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 72 #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 73 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 74 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 75 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 76 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 77 #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 78 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 79 #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 80 #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 81 #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 82 #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 83 #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 84 #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 85 #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 86 #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 87 #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 88 89 90 /*---------------------------------------------------------------------- 91 MISC 92 ----------------------------------------------------------------------*/ 93 94 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 95 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 96 #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 97 /* In T1050, applies to selected core load and store instructions (see ISA): */ 98 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 99 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 100 #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 101 #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 102 103 #define XCHAL_SW_VERSION 900001 /* sw version of this header */ 104 105 #define XCHAL_CORE_ID "dc233c" /* alphanum core name 106 (CoreID) set in the Xtensa 107 Processor Generator */ 108 109 #define XCHAL_CORE_DESCRIPTION "dc233c" 110 #define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ 111 112 /* 113 * These definitions describe the hardware targeted by this software. 114 */ 115 #define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ 116 #define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ 117 #define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ 118 #define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ 119 #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 120 #define XCHAL_HW_VERSION 240001 /* major*100+minor */ 121 #define XCHAL_HW_REL_LX4 1 122 #define XCHAL_HW_REL_LX4_0 1 123 #define XCHAL_HW_REL_LX4_0_1 1 124 #define XCHAL_HW_CONFIGID_RELIABLE 1 125 /* If software targets a *range* of hardware versions, these are the bounds: */ 126 #define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ 127 #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 128 #define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ 129 #define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ 130 #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 131 #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ 132 133 134 /*---------------------------------------------------------------------- 135 CACHE 136 ----------------------------------------------------------------------*/ 137 138 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 139 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 140 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 141 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 142 143 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 144 #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 145 146 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 147 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 148 149 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 150 151 152 /**************************************************************************** 153 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 154 ****************************************************************************/ 155 156 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 157 158 /*---------------------------------------------------------------------- 159 CACHE 160 ----------------------------------------------------------------------*/ 161 162 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 163 164 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 165 166 /* Number of cache sets in log2(lines per way): */ 167 #define XCHAL_ICACHE_SETWIDTH 7 168 #define XCHAL_DCACHE_SETWIDTH 7 169 170 /* Cache set associativity (number of ways): */ 171 #define XCHAL_ICACHE_WAYS 4 172 #define XCHAL_DCACHE_WAYS 4 173 174 /* Cache features: */ 175 #define XCHAL_ICACHE_LINE_LOCKABLE 1 176 #define XCHAL_DCACHE_LINE_LOCKABLE 1 177 #define XCHAL_ICACHE_ECC_PARITY 0 178 #define XCHAL_DCACHE_ECC_PARITY 0 179 180 /* Cache access size in bytes (affects operation of SICW instruction): */ 181 #define XCHAL_ICACHE_ACCESS_SIZE 4 182 #define XCHAL_DCACHE_ACCESS_SIZE 4 183 184 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 185 #define XCHAL_CA_BITS 4 186 187 188 /*---------------------------------------------------------------------- 189 INTERNAL I/D RAM/ROMs and XLMI 190 ----------------------------------------------------------------------*/ 191 192 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 193 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 194 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 195 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 196 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 197 #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 198 199 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 200 201 202 /*---------------------------------------------------------------------- 203 INTERRUPTS and TIMERS 204 ----------------------------------------------------------------------*/ 205 206 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 207 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 208 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 209 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 210 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 211 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 212 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 213 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 214 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 215 (not including level zero) */ 216 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 217 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 218 219 /* Masks of interrupts at each interrupt level: */ 220 #define XCHAL_INTLEVEL1_MASK 0x001F80FF 221 #define XCHAL_INTLEVEL2_MASK 0x00000100 222 #define XCHAL_INTLEVEL3_MASK 0x00200E00 223 #define XCHAL_INTLEVEL4_MASK 0x00001000 224 #define XCHAL_INTLEVEL5_MASK 0x00002000 225 #define XCHAL_INTLEVEL6_MASK 0x00000000 226 #define XCHAL_INTLEVEL7_MASK 0x00004000 227 228 /* Masks of interrupts at each range 1..n of interrupt levels: */ 229 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 230 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 231 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 232 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 233 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 234 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 235 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 236 237 /* Level of each interrupt: */ 238 #define XCHAL_INT0_LEVEL 1 239 #define XCHAL_INT1_LEVEL 1 240 #define XCHAL_INT2_LEVEL 1 241 #define XCHAL_INT3_LEVEL 1 242 #define XCHAL_INT4_LEVEL 1 243 #define XCHAL_INT5_LEVEL 1 244 #define XCHAL_INT6_LEVEL 1 245 #define XCHAL_INT7_LEVEL 1 246 #define XCHAL_INT8_LEVEL 2 247 #define XCHAL_INT9_LEVEL 3 248 #define XCHAL_INT10_LEVEL 3 249 #define XCHAL_INT11_LEVEL 3 250 #define XCHAL_INT12_LEVEL 4 251 #define XCHAL_INT13_LEVEL 5 252 #define XCHAL_INT14_LEVEL 7 253 #define XCHAL_INT15_LEVEL 1 254 #define XCHAL_INT16_LEVEL 1 255 #define XCHAL_INT17_LEVEL 1 256 #define XCHAL_INT18_LEVEL 1 257 #define XCHAL_INT19_LEVEL 1 258 #define XCHAL_INT20_LEVEL 1 259 #define XCHAL_INT21_LEVEL 3 260 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 261 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 262 #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 263 EXCSAVE/EPS/EPC_n, RFI n) */ 264 265 /* Type of each interrupt: */ 266 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 267 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 268 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 269 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 270 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 271 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 272 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 273 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 274 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 275 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 276 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 277 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 278 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 279 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 280 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 281 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 282 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 283 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 284 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 285 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 286 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 287 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 288 289 /* Masks of interrupts for each type of interrupt: */ 290 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 291 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 292 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 293 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 294 #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 295 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 296 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 297 298 /* Interrupt numbers assigned to specific interrupt sources: */ 299 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 300 #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 301 #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 302 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 303 #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 304 305 /* Interrupt numbers for levels at which only one interrupt is configured: */ 306 #define XCHAL_INTLEVEL2_NUM 8 307 #define XCHAL_INTLEVEL4_NUM 12 308 #define XCHAL_INTLEVEL5_NUM 13 309 #define XCHAL_INTLEVEL7_NUM 14 310 /* (There are many interrupts each at level(s) 1, 3.) */ 311 312 313 /* 314 * External interrupt vectors/levels. 315 * These macros describe how Xtensa processor interrupt numbers 316 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 317 * map to external BInterrupt<n> pins, for those interrupts 318 * configured as external (level-triggered, edge-triggered, or NMI). 319 * See the Xtensa processor databook for more details. 320 */ 321 322 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 323 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 324 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 325 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 326 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 327 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 328 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 329 #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 330 #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 331 #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 332 #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 333 #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 334 #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 335 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 336 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 337 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 338 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 339 #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 340 341 342 /*---------------------------------------------------------------------- 343 EXCEPTIONS and VECTORS 344 ----------------------------------------------------------------------*/ 345 346 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 347 number: 1 == XEA1 (old) 348 2 == XEA2 (new) 349 0 == XEAX (extern) or TX */ 350 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 351 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 352 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 353 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 354 #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 355 #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 356 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 357 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 358 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 359 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 360 #define XCHAL_VECBASE_RESET_PADDR 0x00002000 361 #define XCHAL_RESET_VECBASE_OVERLAP 0 362 363 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 364 #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 365 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 366 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 367 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 368 #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 369 #define XCHAL_USER_VECOFS 0x00000340 370 #define XCHAL_USER_VECTOR_VADDR 0x00002340 371 #define XCHAL_USER_VECTOR_PADDR 0x00002340 372 #define XCHAL_KERNEL_VECOFS 0x00000300 373 #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 374 #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 375 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 376 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 377 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 378 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 379 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 380 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 381 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 382 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 383 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 384 #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 385 #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 386 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 387 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 388 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 389 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 390 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 391 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 392 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 393 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 394 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 395 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 396 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 397 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 398 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 399 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 400 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 401 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 402 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 403 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 404 #define XCHAL_NMI_VECOFS 0x000002C0 405 #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 406 #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 407 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 408 #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 409 #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 410 411 412 /*---------------------------------------------------------------------- 413 DEBUG 414 ----------------------------------------------------------------------*/ 415 416 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 417 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 418 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 419 #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 420 421 422 /*---------------------------------------------------------------------- 423 MMU 424 ----------------------------------------------------------------------*/ 425 426 /* See core-matmap.h header file for more details. */ 427 428 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 429 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 430 #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 431 #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 432 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 433 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 434 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 435 #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 436 [autorefill] and protection) 437 usable for an MMU-based OS */ 438 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 439 #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 440 #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 441 442 #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 443 #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 444 #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 445 446 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 447 448 449 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 450