1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for BuR BRPPT2 board
4 *
5 * Copyright (C) 2019
6 * B&R Industrial Automation GmbH - http://www.br-automation.com/
7 *
8 */
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <hang.h>
12 #include <init.h>
13 #include <spl.h>
14 #include <dm.h>
15 #include <miiphy.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #ifdef CONFIG_SPL_BUILD
21 # include <asm/arch/mx6-ddr.h>
22 #endif
23 #include <asm/arch/clock.h>
24 #include <asm/global_data.h>
25 #include <asm/io.h>
26 #include <asm/gpio.h>
27
28 #define USBHUB_RSTN IMX_GPIO_NR(1, 16)
29 #define BKLT_EN IMX_GPIO_NR(1, 15)
30 #define CAPT_INT IMX_GPIO_NR(4, 9)
31 #define CAPT_RESETN IMX_GPIO_NR(4, 11)
32 #define SW_INTN IMX_GPIO_NR(3, 26)
33 #define VCCDISP_EN IMX_GPIO_NR(5, 18)
34 #define EMMC_RSTN IMX_GPIO_NR(6, 8)
35 #define PMIC_IRQN IMX_GPIO_NR(5, 22)
36 #define TASTER IMX_GPIO_NR(5, 23)
37
38 #define ETH0_LINK IMX_GPIO_NR(1, 27)
39 #define ETH1_LINK IMX_GPIO_NR(1, 28)
40
41 #define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
43 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
44
45 #define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
47 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
48
49 #define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
51 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
53 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
54 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
55
56 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
58 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
59
60 #define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
62 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
63
64 #define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
66 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
67
68 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
69 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
70 PAD_CTL_SRE_FAST)
71
72 #define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
73 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
74 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
75
76 #define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
77 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
78 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
79
80 #define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
81 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
82 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
83
84 #define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
85
86 #if !defined(CONFIG_SPL_BUILD)
87 static iomux_v3_cfg_t const eth_pads[] = {
88 /*
89 * Gigabit Ethernet
90 */
91 /* CLKs */
92 MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
93 MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
94 /* MDIO */
95 MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
96 MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
97 /* RGMII */
98 MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
99 MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
100 MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
101 MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
102 MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
103 MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
104 MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
105 MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
106 MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
107 MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
108 MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
109 MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
110 /* ETH0_LINK */
111 MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
112 /* ETH1_LINK */
113 MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
114 };
115
116 static iomux_v3_cfg_t const board_pads[] = {
117 /*
118 * I2C #3, #4
119 */
120 MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
121 MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
122
123 /*
124 * UART#4 PADS
125 * UART_Tasten
126 */
127 MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
128 MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
129 MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
130 MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
131 /*
132 * ESCPI#1
133 * M25P32 NOR-Flash
134 */
135 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
136 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
137 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
138 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
139 /*
140 * ESCPI#2
141 * resTouch SPI ADC
142 */
143 MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
144 MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
145 MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
146 MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
147 /*
148 * USDHC#4
149 */
150 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
151 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
152 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
153 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
154 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
155 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
156 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
157 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
158 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
159 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
160 /*
161 * USB OTG power & ID
162 */
163 /* USB_OTG_5V_EN */
164 MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
165 MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
166 /* USB_OTG_JUMPER */
167 MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
168 /*
169 * PWM-Pins
170 */
171 /* BKLT_CTL */
172 MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
173 /* SPEAKER */
174 MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
175 /*
176 * GPIOs
177 */
178 /* USB_HUB_nRESET */
179 MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
180 /* BKLT_EN */
181 MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
182 /* capTouch_INT */
183 MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
184 /* capTouch_nRESET */
185 MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
186 /* SW_nINT */
187 MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
188 /* VCC_DISP_EN */
189 MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
190 /* eMMC_nRESET */
191 MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
192 /* HWID*/
193 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
194 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
195 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
196 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
197 /* PMIC_nIRQ */
198 MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
199 /* nTASTER */
200 MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
201 /* RGB LCD Display */
202 MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
203 MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
204 MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
205 MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
206 MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
207 MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
208 MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
209 MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
210 MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
211 MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
212 MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
213 MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
214 MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
215 MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
216 MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
217 MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
218 MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
219 MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
220 MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
221 MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
222 MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
223 MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
224 MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
225 MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
226 MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
227 MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
228 MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
229 MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
230 MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
231 };
232
board_ehci_hcd_init(int port)233 int board_ehci_hcd_init(int port)
234 {
235 gpio_direction_output(USBHUB_RSTN, 1);
236
237 return 0;
238 }
239
board_late_init(void)240 int board_late_init(void)
241 {
242 ulong b_mode = 4;
243
244 if (gpio_get_value(TASTER) == 0)
245 b_mode = 12;
246
247 env_set_ulong("b_mode", b_mode);
248
249 return 0;
250 }
251
board_init(void)252 int board_init(void)
253 {
254 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
255
256 if (gpio_request(BKLT_EN, "BKLT_EN"))
257 printf("Warning: BKLT_EN setup failed\n");
258 gpio_direction_output(BKLT_EN, 0);
259
260 if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
261 printf("Warning: USBHUB_nRST setup failed\n");
262 gpio_direction_output(USBHUB_RSTN, 0);
263
264 if (gpio_request(TASTER, "TASTER"))
265 printf("Warning: TASTER setup failed\n");
266 gpio_direction_input(TASTER);
267
268 return 0;
269 }
270
board_early_init_f(void)271 int board_early_init_f(void)
272 {
273 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
274
275 SETUP_IOMUX_PADS(board_pads);
276 SETUP_IOMUX_PADS(eth_pads);
277
278 /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
279 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
280 enable_fec_anatop_clock(0, ENET_25MHZ);
281 enable_enet_clk(1);
282
283 return 0;
284 }
285
dram_init(void)286 int dram_init(void)
287 {
288 gd->ram_size = imx_ddr_size();
289
290 return 0;
291 }
292 #else
293 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
294 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
295 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
296 .dram_sdclk_0 = 0x00020030,
297 .dram_sdclk_1 = 0x00020030,
298 .dram_cas = 0x00020030,
299 .dram_ras = 0x00020030,
300 .dram_reset = 0x00020030,
301 /* SDCKE[0:1]: 100k pull-up */
302 .dram_sdcke0 = 0x00003000,
303 .dram_sdcke1 = 0x00003000,
304 /* SDBA2: pull-up disabled */
305 .dram_sdba2 = 0x00000000,
306 /* SDODT[0:1]: 100k pull-up, 40 ohm */
307 .dram_sdodt0 = 0x00003030,
308 .dram_sdodt1 = 0x00003030,
309 /* SDQS[0:7]: Differential input, 40 ohm */
310 .dram_sdqs0 = 0x00000030,
311 .dram_sdqs1 = 0x00000030,
312 .dram_sdqs2 = 0x00000030,
313 .dram_sdqs3 = 0x00000030,
314 .dram_sdqs4 = 0x00000030,
315 .dram_sdqs5 = 0x00000030,
316 .dram_sdqs6 = 0x00000030,
317 .dram_sdqs7 = 0x00000030,
318 /* DQM[0:7]: Differential input, 40 ohm */
319 .dram_dqm0 = 0x00020030,
320 .dram_dqm1 = 0x00020030,
321 .dram_dqm2 = 0x00020030,
322 .dram_dqm3 = 0x00020030,
323 .dram_dqm4 = 0x00020030,
324 .dram_dqm5 = 0x00020030,
325 .dram_dqm6 = 0x00020030,
326 .dram_dqm7 = 0x00020030,
327 };
328
329 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
330 static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
331 /* DDR3 */
332 .grp_ddr_type = 0x000c0000,
333 .grp_ddrmode_ctl = 0x00020000,
334 /* disable DDR pullups */
335 .grp_ddrpke = 0x00000000,
336 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
337 .grp_addds = 0x00000030,
338 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
339 .grp_ctlds = 0x00000030,
340 /* DATA[00:63]: Differential input, 40 ohm */
341 .grp_ddrmode = 0x00020000,
342 .grp_b0ds = 0x00000030,
343 .grp_b1ds = 0x00000030,
344 .grp_b2ds = 0x00000030,
345 .grp_b3ds = 0x00000030,
346 .grp_b4ds = 0x00000030,
347 .grp_b5ds = 0x00000030,
348 .grp_b6ds = 0x00000030,
349 .grp_b7ds = 0x00000030,
350 };
351
352 /*
353 * DDR3 desriptions - these are the memory chips we support
354 */
355
356 /* NT5CC128M16FP-DII */
357 static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
358 .mem_speed = 1600,
359 .density = 2,
360 .width = 16,
361 .banks = 8,
362 .rowaddr = 14,
363 .coladdr = 10,
364 .pagesz = 2,
365 .trcd = 1375,
366 .trcmin = 4875,
367 .trasmin = 3500,
368 };
369
370 /* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
371 static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
372 /* write leveling calibration determine, MR1-value = 0x0002 */
373 .p0_mpwldectrl0 = 0x003F003E,
374 .p0_mpwldectrl1 = 0x003A003A,
375 .p1_mpwldectrl0 = 0x001B001C,
376 .p1_mpwldectrl1 = 0x00190031,
377 /* Read DQS Gating calibration */
378 .p0_mpdgctrl0 = 0x02640264,
379 .p0_mpdgctrl1 = 0x02440250,
380 .p1_mpdgctrl0 = 0x02400250,
381 .p1_mpdgctrl1 = 0x0238023C,
382 /* Read Calibration: DQS delay relative to DQ read access */
383 .p0_mprddlctl = 0x40464644,
384 .p1_mprddlctl = 0x464A4842,
385 /* Write Calibration: DQ/DM delay relative to DQS write access */
386 .p0_mpwrdlctl = 0x38343034,
387 .p1_mpwrdlctl = 0x36323830,
388 };
389
390 /* measured on board TSERIES_ARM/1 V_LVDS_S32 */
391 static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
392 /* write leveling calibration determine, MR1-value = 0x0002 */
393 .p0_mpwldectrl0 = 0x00410043,
394 .p0_mpwldectrl1 = 0x003A003C,
395 /* Read DQS Gating calibration */
396 .p0_mpdgctrl0 = 0x023C0244,
397 .p0_mpdgctrl1 = 0x02240230,
398 /* Read Calibration: DQS delay relative to DQ read access */
399 .p0_mprddlctl = 0x484C4A48,
400 /* Write Calibration: DQ/DM delay relative to DQS write access */
401 .p0_mpwrdlctl = 0x3C363434,
402 };
403
spl_dram_init(void)404 static void spl_dram_init(void)
405 {
406 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
407 u32 val, dram_strap = 0;
408 struct mx6_ddr3_cfg *mem = NULL;
409 struct mx6_mmdc_calibration *calib = NULL;
410 struct mx6_ddr_sysinfo sysinfo = {
411 /* width of data bus:0=16,1=32,2=64 */
412 .dsize = -1, /* CPU type specific (overwritten) */
413 /* config for full 4GB range so that get_mem_size() works */
414 .cs_density = 32, /* 32Gb per CS */
415 .ncs = 1, /* single chip select */
416 .cs1_mirror = 0,
417 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
418 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
419 .walat = 1, /* Write additional latency */
420 .ralat = 5, /* Read additional latency */
421 .mif3_mode = 3, /* Command prediction working mode */
422 .bi_on = 1, /* Bank interleaving enabled */
423 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
424 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
425 .ddr_type = 0, /* DDR3 */
426 };
427
428 /*
429 * MMDC Calibration requires the following data:
430 * mx6_mmdc_calibration - board-specific calibration (routing delays)
431 * these calibration values depend on board routing, SoC, and DDR
432 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
433 * mx6_ddr_cfg - chip specific timing/layout details
434 */
435
436 /* setup HWID3-2 to input */
437 val = readl(&gpio->gpio_dir);
438 val &= ~(0x1 << 0 | 0x1 << 1);
439 writel(val, &gpio->gpio_dir);
440
441 /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
442 dram_strap = readl(&gpio->gpio_psr) & 0x3;
443
444 switch (dram_strap) {
445 /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
446 case 0:
447 puts("DRAM strap 00\n");
448 mem = &cfg_nt5cc128m16fp_dii;
449 sysinfo.dsize = 2;
450 calib = &cal_nt5cc128m16fp_dii_128x64_s;
451 break;
452 /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
453 case 1:
454 puts("DRAM strap 01\n");
455 mem = &cfg_nt5cc128m16fp_dii;
456 sysinfo.dsize = 1;
457 calib = &cal_nt5cc128m16fp_dii_128x32_s;
458 break;
459 default:
460 printf("DRAM strap 0x%x (invalid)\n", dram_strap);
461 break;
462 }
463
464 if (!mem) {
465 puts("Error: Invalid Memory Configuration\n");
466 hang();
467 }
468 if (!calib) {
469 puts("Error: Invalid Board Calibration Configuration\n");
470 hang();
471 }
472
473 mx6sdl_dram_iocfg(16 << sysinfo.dsize,
474 &ddr_iomux_s,
475 &grp_iomux_s);
476
477 mx6_dram_cfg(&sysinfo, calib, mem);
478 }
479
480 static iomux_v3_cfg_t const board_pads_spl[] = {
481 /* UART#1 PADS */
482 MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
483 MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
484 /* ESCPI#1 PADS */
485 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
486 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
487 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
488 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
489 /* USDHC#4 PADS */
490 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
491 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
492 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
493 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
494 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
495 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
496 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
497 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
498 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
499 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
500 /* HWID*/
501 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
502 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
503 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
504 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
505 };
506
spl_board_init(void)507 void spl_board_init(void)
508 {
509 preloader_console_init();
510 }
511
ccgr_init(void)512 static void ccgr_init(void)
513 {
514 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
515
516 /*
517 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
518 * initializes DMA very early (before all board code), so the only
519 * opportunity we have to initialize APBHDMA clocks is in SPL.
520 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
521 */
522
523 writel(0x00C03F3F, &ccm->CCGR0);
524 writel(0x00F0FC03, &ccm->CCGR1);
525 writel(0x0FFFF000, &ccm->CCGR2);
526 writel(0x3FF00000, &ccm->CCGR3);
527 writel(0x00FFF300, &ccm->CCGR4);
528 writel(0x0F0030C3, &ccm->CCGR5);
529 writel(0x000003F0, &ccm->CCGR6);
530 }
531
board_init_f(ulong dummy)532 void board_init_f(ulong dummy)
533 {
534 ccgr_init();
535 arch_cpu_init();
536 timer_init();
537 gpr_init();
538
539 SETUP_IOMUX_PADS(board_pads_spl);
540 spl_dram_init();
541 }
542
reset_cpu(void)543 void reset_cpu(void)
544 {
545 }
546 #endif /* CONFIG_SPL_BUILD */
547