1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 */
18 #include <common.h>
19 #include <bootstage.h>
20 #include <cpu_func.h>
21 #include <init.h>
22 #include <malloc.h>
23 #include <errno.h>
24 #include <net.h>
25 #include <netdev.h>
26 #include <asm/global_data.h>
27 #include <asm/io.h>
28 #include <asm/mach-types.h>
29 #include <asm/arch/systimer.h>
30 #include <asm/arch/sysctrl.h>
31 #include <asm/arch/wdt.h>
32
33 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
34 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
35
36 static void flash__init(void);
37 static void vexpress_timer_init(void);
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)41 void show_boot_progress(int progress)
42 {
43 printf("Boot reached stage %d\n", progress);
44 }
45 #endif
46
delay(ulong loops)47 static inline void delay(ulong loops)
48 {
49 __asm__ volatile ("1:\n"
50 "subs %0, %1, #1\n"
51 "bne 1b" : "=r" (loops) : "0" (loops));
52 }
53
board_init(void)54 int board_init(void)
55 {
56 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
57 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
58
59 icache_enable();
60 flash__init();
61 vexpress_timer_init();
62
63 return 0;
64 }
65
flash__init(void)66 static void flash__init(void)
67 {
68 /* Setup the sytem control register to allow writing to flash */
69 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
70 &sysctrl_base->scflashctrl);
71 }
72
dram_init(void)73 int dram_init(void)
74 {
75 gd->ram_size =
76 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
77 return 0;
78 }
79
dram_init_banksize(void)80 int dram_init_banksize(void)
81 {
82 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
83 gd->bd->bi_dram[0].size =
84 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
85 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
86 gd->bd->bi_dram[1].size =
87 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
88
89 return 0;
90 }
91
92 /*
93 * Start timer:
94 * Setup a 32 bit timer, running at 1KHz
95 * Versatile Express Motherboard provides 1 MHz timer
96 */
vexpress_timer_init(void)97 static void vexpress_timer_init(void)
98 {
99 /*
100 * Set clock frequency in system controller:
101 * VEXPRESS_REFCLK is 32KHz
102 * VEXPRESS_TIMCLK is 1MHz
103 */
104 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
105 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
106 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
107
108 /*
109 * Set Timer0 to be:
110 * Enabled, free running, no interrupt, 32-bit, wrapping
111 */
112 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
113 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
114 writel(SYSTIMER_EN | SYSTIMER_32BIT |
115 readl(&systimer_base->timer0control),
116 &systimer_base->timer0control);
117 }
118
v2m_cfg_write(u32 devfn,u32 data)119 int v2m_cfg_write(u32 devfn, u32 data)
120 {
121 /* Configuration interface broken? */
122 u32 val;
123
124 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
125
126 val = readl(V2M_SYS_CFGSTAT);
127 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
128
129 writel(data, V2M_SYS_CFGDATA);
130 writel(devfn, V2M_SYS_CFGCTRL);
131
132 do {
133 val = readl(V2M_SYS_CFGSTAT);
134 } while (val == 0);
135
136 return !!(val & SYS_CFG_ERR);
137 }
138
139 /* Use the ARM Watchdog System to cause reset */
reset_cpu(void)140 void reset_cpu(void)
141 {
142 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
143 printf("Unable to reboot\n");
144 }
145
lowlevel_init(void)146 void lowlevel_init(void)
147 {
148 }
149
get_board_rev(void)150 ulong get_board_rev(void){
151 return readl((u32 *)SYS_ID);
152 }
153
154 #ifdef CONFIG_ARMV7_NONSEC
155 /* Setting the address at which secondary cores start from.
156 * Versatile Express uses one address for all cores, so ignore corenr
157 */
smp_set_core_boot_addr(unsigned long addr,int corenr)158 void smp_set_core_boot_addr(unsigned long addr, int corenr)
159 {
160 /* The SYSFLAGS register on VExpress needs to be cleared first
161 * by writing to the next address, since any writes to the address
162 * at offset 0 will only be ORed in
163 */
164 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
165 writel(addr, CONFIG_SYSFLAGS_ADDR);
166 }
167 #endif
168