1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Atmel Corporation
4 * Josh Wu <josh.wu@atmel.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <net.h>
10 #include <vsprintf.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/at91sam9x5_matrix.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/at91_rstc.h>
17 #include <asm/arch/at91_pio.h>
18 #include <asm/arch/clk.h>
19 #include <debug_uart.h>
20 #include <lcd.h>
21 #include <atmel_hlcdc.h>
22 #include <netdev.h>
23
24 #ifdef CONFIG_LCD_INFO
25 #include <nand.h>
26 #include <version.h>
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* ------------------------------------------------------------------------- */
32 /*
33 * Miscelaneous platform dependent initialisations
34 */
35 #ifdef CONFIG_NAND_ATMEL
at91sam9n12ek_nand_hw_init(void)36 static void at91sam9n12ek_nand_hw_init(void)
37 {
38 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
39 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
40 unsigned long csa;
41
42 /* Assign CS3 to NAND/SmartMedia Interface */
43 csa = readl(&matrix->ebicsa);
44 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
45 /* Configure databus */
46 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
47 /* Configure IO drive */
48 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
49
50 writel(csa, &matrix->ebicsa);
51
52 /* Configure SMC CS3 for NAND/SmartMedia */
53 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
54 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
55 &smc->cs[3].setup);
56 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
57 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
58 &smc->cs[3].pulse);
59 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
60 &smc->cs[3].cycle);
61 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
62 AT91_SMC_MODE_EXNW_DISABLE |
63 #ifdef CONFIG_SYS_NAND_DBW_16
64 AT91_SMC_MODE_DBW_16 |
65 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_DBW_8 |
67 #endif
68 AT91_SMC_MODE_TDF_CYCLE(1),
69 &smc->cs[3].mode);
70
71 /* Configure RDY/BSY pin */
72 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
73
74 /* Configure ENABLE pin for NandFlash */
75 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
76
77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
80 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
81 }
82 #endif
83
84 #ifdef CONFIG_LCD
85 vidinfo_t panel_info = {
86 .vl_col = 480,
87 .vl_row = 272,
88 .vl_clk = 9000000,
89 .vl_bpix = LCD_BPP,
90 .vl_sync = 0,
91 .vl_tft = 1,
92 .vl_hsync_len = 5,
93 .vl_left_margin = 8,
94 .vl_right_margin = 43,
95 .vl_vsync_len = 10,
96 .vl_upper_margin = 4,
97 .vl_lower_margin = 12,
98 .mmio = ATMEL_BASE_LCDC,
99 };
100
lcd_enable(void)101 void lcd_enable(void)
102 {
103 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
104 }
105
lcd_disable(void)106 void lcd_disable(void)
107 {
108 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
109 }
110
111 #ifdef CONFIG_LCD_INFO
lcd_show_board_info(void)112 void lcd_show_board_info(void)
113 {
114 ulong dram_size, nand_size;
115 int i;
116 char temp[32];
117
118 lcd_printf("%s\n", U_BOOT_VERSION);
119 lcd_printf("ATMEL Corp\n");
120 lcd_printf("at91@atmel.com\n");
121 lcd_printf("%s CPU at %s MHz\n",
122 ATMEL_CPU_NAME,
123 strmhz(temp, get_cpu_clk_rate()));
124
125 dram_size = 0;
126 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
127 dram_size += gd->bd->bi_dram[i].size;
128 nand_size = 0;
129 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
130 nand_size += get_nand_dev_by_index(i)->size;
131 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
132 dram_size >> 20,
133 nand_size >> 20);
134 }
135 #endif /* CONFIG_LCD_INFO */
136 #endif /* CONFIG_LCD */
137
138 #ifdef CONFIG_KS8851_MLL
at91sam9n12ek_ks8851_hw_init(void)139 void at91sam9n12ek_ks8851_hw_init(void)
140 {
141 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
142
143 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
144 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
145 &smc->cs[2].setup);
146 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
147 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
148 &smc->cs[2].pulse);
149 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
150 &smc->cs[2].cycle);
151 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
152 AT91_SMC_MODE_EXNW_DISABLE |
153 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
154 AT91_SMC_MODE_TDF_CYCLE(1),
155 &smc->cs[2].mode);
156
157 /* Configure NCS2 PIN */
158 at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
159 }
160 #endif
161
162 #ifdef CONFIG_USB_ATMEL
at91sam9n12ek_usb_hw_init(void)163 void at91sam9n12ek_usb_hw_init(void)
164 {
165 at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
166 }
167 #endif
168
169 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)170 void board_debug_uart_init(void)
171 {
172 at91_seriald_hw_init();
173 }
174 #endif
175
176 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)177 int board_early_init_f(void)
178 {
179 #ifdef CONFIG_DEBUG_UART
180 debug_uart_init();
181 #endif
182 return 0;
183 }
184 #endif
185
board_init(void)186 int board_init(void)
187 {
188 /* adress of boot parameters */
189 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
190
191 #ifdef CONFIG_NAND_ATMEL
192 at91sam9n12ek_nand_hw_init();
193 #endif
194
195 #ifdef CONFIG_LCD
196 at91_lcd_hw_init();
197 #endif
198
199 #ifdef CONFIG_KS8851_MLL
200 at91sam9n12ek_ks8851_hw_init();
201 #endif
202
203 #ifdef CONFIG_USB_ATMEL
204 at91sam9n12ek_usb_hw_init();
205 #endif
206
207 return 0;
208 }
209
210 #ifdef CONFIG_KS8851_MLL
board_eth_init(struct bd_info * bis)211 int board_eth_init(struct bd_info *bis)
212 {
213 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
214 }
215 #endif
216
dram_init(void)217 int dram_init(void)
218 {
219 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
220 CONFIG_SYS_SDRAM_SIZE);
221 return 0;
222 }
223
224 #if defined(CONFIG_SPL_BUILD)
225 #include <spl.h>
226 #include <nand.h>
227
at91_spl_board_init(void)228 void at91_spl_board_init(void)
229 {
230 #ifdef CONFIG_SD_BOOT
231 at91_mci_hw_init();
232 #elif CONFIG_NAND_BOOT
233 at91sam9n12ek_nand_hw_init();
234 #elif CONFIG_SPI_BOOT
235 at91_spi0_hw_init(1 << 4);
236 #endif
237 }
238
239 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)240 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
241 {
242 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
243
244 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
245 ATMEL_MPDDRC_CR_NR_ROW_13 |
246 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
247 ATMEL_MPDDRC_CR_NB_8BANKS |
248 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
249
250 ddr2->rtr = 0x411;
251
252 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
253 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
254 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
255 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
256 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
257 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
258 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
259 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
260
261 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
262 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
263 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
264 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
265
266 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
267 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
268 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
269 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
270 }
271
mem_init(void)272 void mem_init(void)
273 {
274 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
275 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
276 struct atmel_mpddrc_config ddr2;
277 unsigned long csa;
278
279 ddr2_conf(&ddr2);
280
281 /* enable DDR2 clock */
282 writel(AT91_PMC_DDR, &pmc->scer);
283
284 /* Chip select 1 is for DDR2/SDRAM */
285 csa = readl(&matrix->ebicsa);
286 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
287 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
288 csa |= AT91_MATRIX_EBI_DBPD_OFF;
289 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
290 writel(csa, &matrix->ebicsa);
291
292 /* DDRAM2 Controller initialize */
293 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
294 }
295 #endif
296