1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Microchip Corporation
4 * Wenyou.Yang <wenyou.yang@microchip.com>
5 */
6
7 #include <common.h>
8 #include <debug_uart.h>
9 #include <fdtdec.h>
10 #include <init.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/atmel_pio4.h>
15 #include <asm/arch/atmel_mpddrc.h>
16 #include <asm/arch/atmel_sdhci.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/sama5d2.h>
20
21 extern void at91_pda_detect(void);
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #ifdef CONFIG_CMD_USB
board_usb_hw_init(void)26 static void board_usb_hw_init(void)
27 {
28 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
29 }
30 #endif
31
32 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)33 int board_late_init(void)
34 {
35 #ifdef CONFIG_DM_VIDEO
36 at91_video_show_board_info();
37 #endif
38 at91_pda_detect();
39 return 0;
40 }
41 #endif
42
43 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_uart1_hw_init(void)44 static void board_uart1_hw_init(void)
45 {
46 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
47 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
48
49 at91_periph_clk_enable(ATMEL_ID_UART1);
50 }
51
board_debug_uart_init(void)52 void board_debug_uart_init(void)
53 {
54 board_uart1_hw_init();
55 }
56 #endif
57
58 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)59 int board_early_init_f(void)
60 {
61 #ifdef CONFIG_DEBUG_UART
62 debug_uart_init();
63 #endif
64
65 return 0;
66 }
67 #endif
68
board_init(void)69 int board_init(void)
70 {
71 /* address of boot parameters */
72 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
73
74 #ifdef CONFIG_CMD_USB
75 board_usb_hw_init();
76 #endif
77
78 return 0;
79 }
80
dram_init_banksize(void)81 int dram_init_banksize(void)
82 {
83 return fdtdec_setup_memory_banksize();
84 }
85
dram_init(void)86 int dram_init(void)
87 {
88 return fdtdec_setup_mem_size_base();
89 }
90
91 #define MAC24AA_MAC_OFFSET 0xfa
92
93 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)94 int misc_init_r(void)
95 {
96 #ifdef CONFIG_I2C_EEPROM
97 at91_set_ethaddr(MAC24AA_MAC_OFFSET);
98 #endif
99 return 0;
100 }
101 #endif
102
103 /* SPL */
104 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)105 void spl_board_init(void)
106 {
107 }
108
ddrc_conf(struct atmel_mpddrc_config * ddrc)109 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
110 {
111 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
112
113 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
114 ATMEL_MPDDRC_CR_NR_ROW_13 |
115 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
116 ATMEL_MPDDRC_CR_DIC_DS |
117 ATMEL_MPDDRC_CR_ZQ_LONG |
118 ATMEL_MPDDRC_CR_NB_8BANKS |
119 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
120 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
121
122 ddrc->rtr = 0x511;
123
124 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
125 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
126 (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
127 (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
128 (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
129 (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
130 (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
131 (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
132
133 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
134 (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
135 (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
136 (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
137
138 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
139 (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
140 (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
141 (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
142 (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
143 }
144
mem_init(void)145 void mem_init(void)
146 {
147 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
148 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
149 struct atmel_mpddrc_config ddrc_config;
150 u32 reg;
151
152 ddrc_conf(&ddrc_config);
153
154 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
155 writel(AT91_PMC_DDR, &pmc->scer);
156
157 reg = readl(&mpddrc->io_calibr);
158 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
159 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
160 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
161 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
162 writel(reg, &mpddrc->io_calibr);
163
164 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
165 &mpddrc->rd_data_path);
166
167 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
168
169 writel(0x3, &mpddrc->cal_mr4);
170 writel(64, &mpddrc->tim_cal);
171 }
172
at91_pmc_init(void)173 void at91_pmc_init(void)
174 {
175 u32 tmp;
176
177 /*
178 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
179 * so we need to slow down and configure MCKR accordingly.
180 * This is why we have a special flavor of the switching function.
181 */
182 tmp = AT91_PMC_MCKR_PLLADIV_2 |
183 AT91_PMC_MCKR_MDIV_3 |
184 AT91_PMC_MCKR_CSS_MAIN;
185 at91_mck_init_down(tmp);
186
187 tmp = AT91_PMC_PLLAR_29 |
188 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
189 AT91_PMC_PLLXR_MUL(40) |
190 AT91_PMC_PLLXR_DIV(1);
191 at91_plla_init(tmp);
192
193 tmp = AT91_PMC_MCKR_H32MXDIV |
194 AT91_PMC_MCKR_PLLADIV_2 |
195 AT91_PMC_MCKR_MDIV_3 |
196 AT91_PMC_MCKR_CSS_PLLA;
197 at91_mck_init(tmp);
198 }
199 #endif
200