1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Atmel
4 * Bo Shen <voice.shen@atmel.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/atmel_mpddrc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/sama5d3_smc.h>
17 #include <asm/arch/sama5d4.h>
18 #include <debug_uart.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init(void)23 static void sama5d4ek_nand_hw_init(void)
24 {
25 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
26
27 at91_periph_clk_enable(ATMEL_ID_SMC);
28
29 /* Configure SMC CS3 for NAND */
30 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
31 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
32 &smc->cs[3].setup);
33 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
34 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
35 &smc->cs[3].pulse);
36 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
37 &smc->cs[3].cycle);
38 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
39 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
40 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
41 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
42 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
43 AT91_SMC_MODE_EXNW_DISABLE |
44 AT91_SMC_MODE_DBW_8 |
45 AT91_SMC_MODE_TDF_CYCLE(3),
46 &smc->cs[3].mode);
47
48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
62 }
63 #endif
64
65 #ifdef CONFIG_CMD_USB
sama5d4ek_usb_hw_init(void)66 static void sama5d4ek_usb_hw_init(void)
67 {
68 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
69 at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
70 at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
71 }
72 #endif
73
74 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)75 int board_late_init(void)
76 {
77 #ifdef CONFIG_DM_VIDEO
78 at91_video_show_board_info();
79 #endif
80 return 0;
81 }
82 #endif
83
84 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
sama5d4ek_serial3_hw_init(void)85 static void sama5d4ek_serial3_hw_init(void)
86 {
87 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
88 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
89
90 /* Enable clock */
91 at91_periph_clk_enable(ATMEL_ID_USART3);
92 }
93
board_debug_uart_init(void)94 void board_debug_uart_init(void)
95 {
96 sama5d4ek_serial3_hw_init();
97 }
98 #endif
99
100 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)101 int board_early_init_f(void)
102 {
103 #ifdef CONFIG_DEBUG_UART
104 debug_uart_init();
105 #endif
106 return 0;
107 }
108 #endif
109
board_init(void)110 int board_init(void)
111 {
112 /* adress of boot parameters */
113 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
114
115 #ifdef CONFIG_NAND_ATMEL
116 sama5d4ek_nand_hw_init();
117 #endif
118 #ifdef CONFIG_CMD_USB
119 sama5d4ek_usb_hw_init();
120 #endif
121
122 return 0;
123 }
124
dram_init(void)125 int dram_init(void)
126 {
127 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
128 CONFIG_SYS_SDRAM_SIZE);
129 return 0;
130 }
131
132 /* SPL */
133 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)134 void spl_board_init(void)
135 {
136 #if CONFIG_NAND_BOOT
137 sama5d4ek_nand_hw_init();
138 #endif
139 }
140
ddr2_conf(struct atmel_mpddrc_config * ddr2)141 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
142 {
143 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
144
145 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
146 ATMEL_MPDDRC_CR_NR_ROW_14 |
147 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
148 ATMEL_MPDDRC_CR_NB_8BANKS |
149 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
150 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
151
152 ddr2->rtr = 0x2b0;
153
154 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
155 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
156 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
157 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
158 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
159 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
160 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
161 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
162
163 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
164 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
165 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
166 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
167
168 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
169 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
170 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
171 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
172 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
173 }
174
mem_init(void)175 void mem_init(void)
176 {
177 struct atmel_mpddrc_config ddr2;
178 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
179 u32 tmp;
180
181 ddr2_conf(&ddr2);
182
183 /* Enable MPDDR clock */
184 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
185 at91_system_clk_enable(AT91_PMC_DDR);
186
187 tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
188 writel(tmp, &mpddr->rd_data_path);
189
190 tmp = readl(&mpddr->io_calibr);
191 tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
192 ATMEL_MPDDRC_IO_CALIBR_TZQIO |
193 ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
194 ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
195 ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
196 ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
197 ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
198 writel(tmp, &mpddr->io_calibr);
199
200 /* DDRAM2 Controller initialize */
201 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
202 }
203
at91_pmc_init(void)204 void at91_pmc_init(void)
205 {
206 u32 tmp;
207
208 tmp = AT91_PMC_PLLAR_29 |
209 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
210 AT91_PMC_PLLXR_MUL(87) |
211 AT91_PMC_PLLXR_DIV(1);
212 at91_plla_init(tmp);
213
214 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
215
216 tmp = AT91_PMC_MCKR_H32MXDIV |
217 AT91_PMC_MCKR_PLLADIV_2 |
218 AT91_PMC_MCKR_MDIV_3 |
219 AT91_PMC_MCKR_CSS_PLLA;
220 at91_mck_init(tmp);
221 }
222 #endif
223