1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * (C) Copyright 2016
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 *
8 * Based on:
9 * Board functions for TI AM335X based boards
10 *
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 */
13
14 #include <common.h>
15 #include <bootstage.h>
16 #include <cpu_func.h>
17 #include <env.h>
18 #include <errno.h>
19 #include <init.h>
20 #include <irq_func.h>
21 #include <net.h>
22 #include <spl.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/omap.h>
26 #include <asm/arch/ddr_defs.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/mem.h>
32 #include <asm/global_data.h>
33 #include <asm/io.h>
34 #include <asm/emif.h>
35 #include <asm/gpio.h>
36 #include <i2c.h>
37 #include <miiphy.h>
38 #include <cpsw.h>
39 #include <linux/delay.h>
40 #include <power/tps65217.h>
41 #include <env_internal.h>
42 #include <watchdog.h>
43 #include "mmc.h"
44 #include "board.h"
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 static struct shc_eeprom __section(".data") header;
49 static int shc_eeprom_valid;
50
51 /*
52 * Read header information from EEPROM into global structure.
53 */
54 #define EEPROM_ADDR 0x50
read_eeprom(void)55 static int read_eeprom(void)
56 {
57 /* Check if baseboard eeprom is available */
58 if (i2c_probe(EEPROM_ADDR)) {
59 puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
60 return -ENODEV;
61 }
62
63 /* read the eeprom using i2c */
64 if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header,
65 sizeof(header))) {
66 puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
67 return -EIO;
68 }
69
70 if (header.magic != HDR_MAGIC) {
71 printf("Incorrect magic number (0x%x) in EEPROM\n",
72 header.magic);
73 return -EIO;
74 }
75
76 shc_eeprom_valid = 1;
77
78 return 0;
79 }
80
shc_request_gpio(void)81 static void shc_request_gpio(void)
82 {
83 gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
84 gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
85 gpio_request(RESET_GPIO, "reset");
86 gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
87 gpio_request(WIFI_RST_GPIO, "WIFI rst");
88 gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
89 gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
90 gpio_request(ENOC_RST_GPIO, "ENOC rst");
91 #if defined CONFIG_B_SAMPLE
92 gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
93 gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
94 gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
95 gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
96 #else
97 gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
98 gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
99 gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
100 gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
101 gpio_request(LED_PWM_GPIO, "LED PWM");
102 gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
103 #endif
104 gpio_request(BACK_BUTTON_GPIO, "Back button");
105 gpio_request(FRONT_BUTTON_GPIO, "Front button");
106 }
107
108 /*
109 * Function which forces all installed modules into running state for ICT
110 * testing. Called by SPL.
111 */
force_modules_running(void)112 static void __maybe_unused force_modules_running(void)
113 {
114 /* Wi-Fi power regulator enable - high = enabled */
115 gpio_direction_output(WIFI_REGEN_GPIO, 1);
116 /*
117 * Wait for Wi-Fi power regulator to reach a stable voltage
118 * (soft-start time, max. 350 µs)
119 */
120 __udelay(350);
121
122 /* Wi-Fi module reset - high = running */
123 gpio_direction_output(WIFI_RST_GPIO, 1);
124
125 /* ZigBee reset - high = running */
126 gpio_direction_output(ZIGBEE_RST_GPIO, 1);
127
128 /* BidCos reset - high = running */
129 gpio_direction_output(BIDCOS_RST_GPIO, 1);
130
131 #if !defined(CONFIG_B_SAMPLE)
132 /* Z-Wave reset - high = running */
133 gpio_direction_output(Z_WAVE_RST_GPIO, 1);
134 #endif
135
136 /* EnOcean reset - low = running */
137 gpio_direction_output(ENOC_RST_GPIO, 0);
138 }
139
140 /*
141 * Function which forces all installed modules into reset - to be released by
142 * the OS, called by SPL
143 */
force_modules_reset(void)144 static void __maybe_unused force_modules_reset(void)
145 {
146 /* Wi-Fi module reset - low = reset */
147 gpio_direction_output(WIFI_RST_GPIO, 0);
148
149 /* Wi-Fi power regulator enable - low = disabled */
150 gpio_direction_output(WIFI_REGEN_GPIO, 0);
151
152 /* ZigBee reset - low = reset */
153 gpio_direction_output(ZIGBEE_RST_GPIO, 0);
154
155 /* BidCos reset - low = reset */
156 /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
157
158 #if !defined(CONFIG_B_SAMPLE)
159 /* Z-Wave reset - low = reset */
160 gpio_direction_output(Z_WAVE_RST_GPIO, 0);
161 #endif
162
163 /* EnOcean reset - high = reset*/
164 gpio_direction_output(ENOC_RST_GPIO, 1);
165 }
166
167 /*
168 * Function to set the LEDs in the state "Bootloader booting"
169 */
leds_set_booting(void)170 static void __maybe_unused leds_set_booting(void)
171 {
172 #if defined(CONFIG_B_SAMPLE)
173
174 /* Turn all red LEDs on */
175 gpio_direction_output(LED_PWR_RD_GPIO, 1);
176 gpio_direction_output(LED_CONN_RD_GPIO, 1);
177
178 #else /* All other SHCs starting with B2-Sample */
179 /* Set the PWM GPIO */
180 gpio_direction_output(LED_PWM_GPIO, 1);
181 /* Turn all red LEDs on */
182 gpio_direction_output(LED_PWR_RD_GPIO, 1);
183 gpio_direction_output(LED_LAN_RD_GPIO, 1);
184 gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
185
186 #endif
187 }
188
189 /*
190 * Function to set the LEDs in the state "Bootloader error"
191 */
leds_set_failure(int state)192 static void __maybe_unused leds_set_failure(int state)
193 {
194 #if defined(CONFIG_B_SAMPLE)
195 /* Turn all blue and green LEDs off */
196 gpio_set_value(LED_PWR_BL_GPIO, 0);
197 gpio_set_value(LED_PWR_GN_GPIO, 0);
198 gpio_set_value(LED_CONN_BL_GPIO, 0);
199 gpio_set_value(LED_CONN_GN_GPIO, 0);
200
201 /* Turn all red LEDs to 'state' */
202 gpio_set_value(LED_PWR_RD_GPIO, state);
203 gpio_set_value(LED_CONN_RD_GPIO, state);
204
205 #else /* All other SHCs starting with B2-Sample */
206 /* Set the PWM GPIO */
207 gpio_direction_output(LED_PWM_GPIO, 1);
208
209 /* Turn all blue LEDs off */
210 gpio_set_value(LED_PWR_BL_GPIO, 0);
211 gpio_set_value(LED_LAN_BL_GPIO, 0);
212 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
213
214 /* Turn all red LEDs to 'state' */
215 gpio_set_value(LED_PWR_RD_GPIO, state);
216 gpio_set_value(LED_LAN_RD_GPIO, state);
217 gpio_set_value(LED_CLOUD_RD_GPIO, state);
218 #endif
219 }
220
221 /*
222 * Function to set the LEDs in the state "Bootloader finished"
223 */
leds_set_finish(void)224 static void leds_set_finish(void)
225 {
226 #if defined(CONFIG_B_SAMPLE)
227 /* Turn all LEDs off */
228 gpio_set_value(LED_PWR_BL_GPIO, 0);
229 gpio_set_value(LED_PWR_RD_GPIO, 0);
230 gpio_set_value(LED_PWR_GN_GPIO, 0);
231 gpio_set_value(LED_CONN_BL_GPIO, 0);
232 gpio_set_value(LED_CONN_RD_GPIO, 0);
233 gpio_set_value(LED_CONN_GN_GPIO, 0);
234 #else /* All other SHCs starting with B2-Sample */
235 /* Turn all LEDs off */
236 gpio_set_value(LED_PWR_BL_GPIO, 0);
237 gpio_set_value(LED_PWR_RD_GPIO, 0);
238 gpio_set_value(LED_LAN_BL_GPIO, 0);
239 gpio_set_value(LED_LAN_RD_GPIO, 0);
240 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
241 gpio_set_value(LED_CLOUD_RD_GPIO, 0);
242
243 /* Turn off the PWM GPIO and mux it to EHRPWM */
244 gpio_set_value(LED_PWM_GPIO, 0);
245 enable_shc_board_pwm_pin_mux();
246 #endif
247 }
248
check_button_status(void)249 static void check_button_status(void)
250 {
251 ulong value;
252 gpio_direction_input(FRONT_BUTTON_GPIO);
253 value = gpio_get_value(FRONT_BUTTON_GPIO);
254
255 if (value == 0) {
256 printf("front button activated !\n");
257 env_set("harakiri", "1");
258 }
259 }
260
261 #if defined(CONFIG_SPL_BUILD)
262 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)263 int spl_start_uboot(void)
264 {
265 return 1;
266 }
267 #endif
268
shc_board_early_init(void)269 static void shc_board_early_init(void)
270 {
271 shc_request_gpio();
272 # ifdef CONFIG_SHC_ICT
273 /* Force all modules into enabled state for ICT testing */
274 force_modules_running();
275 # else
276 /* Force all modules to enter Reset state until released by the OS */
277 force_modules_reset();
278 # endif
279 leds_set_booting();
280 }
281
282 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
283
284 #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
285 #define OSC (V_OSCK/1000000)
286 /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
287 #define MPUPLL_N (4-1)
288 /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
289 #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
290
291 const struct dpll_params dpll_ddr_shc = {
292 400, OSC-1, 1, -1, -1, -1, -1};
293
get_dpll_ddr_params(void)294 const struct dpll_params *get_dpll_ddr_params(void)
295 {
296 return &dpll_ddr_shc;
297 }
298
299 /*
300 * As we enabled downspread SSC with 1.8%, the values needed to be corrected
301 * such that the 20% overshoot will not lead to too high frequencies.
302 * In all cases, this is achieved by subtracting one from M (6 MHz less).
303 * Example: 600 MHz CPU
304 * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
305 * 600 MHz - 6 MHz (1x Fref) = 594 MHz
306 * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
307 * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
308 * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
309 */
310 const struct dpll_params dpll_mpu_shc_opp100 = {
311 99, MPUPLL_N, 1, -1, -1, -1, -1};
312
am33xx_spl_board_init(void)313 void am33xx_spl_board_init(void)
314 {
315 int sil_rev;
316 int mpu_vdd;
317
318 puts(BOARD_ID_STR);
319
320 /*
321 * Set CORE Frequency to OPP100
322 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
323 */
324 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
325
326 sil_rev = readl(&cdev->deviceid) >> 28;
327 if (sil_rev < 2) {
328 puts("We do not support Silicon Revisions below 2.0!\n");
329 return;
330 }
331
332 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
333 if (i2c_probe(TPS65217_CHIP_PM))
334 return;
335
336 /*
337 * Retrieve the CPU max frequency by reading the efuse
338 * SHC-Default: 600 MHz
339 */
340 switch (dpll_mpu_opp100.m) {
341 case MPUPLL_M_1000:
342 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
343 break;
344 case MPUPLL_M_800:
345 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
346 break;
347 case MPUPLL_M_720:
348 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
349 break;
350 case MPUPLL_M_600:
351 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
352 break;
353 case MPUPLL_M_300:
354 mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
355 break;
356 default:
357 puts("Cannot determine the frequency, failing!\n");
358 return;
359 }
360
361 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
362 puts("tps65217_voltage_update failure\n");
363 return;
364 }
365
366 /* Set MPU Frequency to what we detected */
367 printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
368 printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
369 dpll_mpu_shc_opp100.m);
370 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
371
372 /* Enable Spread Spectrum for this freq to be clean on EMI side */
373 set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
374
375 /*
376 * Using the default voltages for the PMIC (TPS65217D)
377 * LS1 = 1.8V (VDD_1V8)
378 * LS2 = 3.3V (VDD_3V3A)
379 * LDO1 = 1.8V (VIO and VRTC)
380 * LDO2 = 3.3V (VDD_3V3AUX)
381 */
382 shc_board_early_init();
383 }
384
set_uart_mux_conf(void)385 void set_uart_mux_conf(void)
386 {
387 enable_uart0_pin_mux();
388 }
389
set_mux_conf_regs(void)390 void set_mux_conf_regs(void)
391 {
392 enable_shc_board_pin_mux();
393 }
394
395 const struct ctrl_ioregs ioregs_evmsk = {
396 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
397 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
398 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
399 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
400 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
401 };
402
403 static const struct ddr_data ddr3_shc_data = {
404 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
405 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
406 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
407 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
408 };
409
410 static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
411 .cmd0csratio = MT41K256M16HA125E_RATIO,
412 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
413
414 .cmd1csratio = MT41K256M16HA125E_RATIO,
415 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
416
417 .cmd2csratio = MT41K256M16HA125E_RATIO,
418 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
419 };
420
421 static struct emif_regs ddr3_shc_emif_reg_data = {
422 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
423 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
424 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
425 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
426 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
427 .zq_config = MT41K256M16HA125E_ZQ_CFG,
428 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
429 PHY_EN_DYN_PWRDN,
430 };
431
sdram_init(void)432 void sdram_init(void)
433 {
434 /* Configure the DDR3 RAM */
435 config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
436 &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
437 }
438 #endif
439
440 /*
441 * Basic board specific setup. Pinmux has been handled already.
442 */
board_init(void)443 int board_init(void)
444 {
445 #if defined(CONFIG_HW_WATCHDOG)
446 hw_watchdog_init();
447 #endif
448 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
449 if (read_eeprom() < 0)
450 puts("EEPROM Content Invalid.\n");
451
452 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
453 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
454 gpmc_init();
455 #endif
456 shc_request_gpio();
457
458 return 0;
459 }
460
461 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)462 int board_late_init(void)
463 {
464 check_button_status();
465 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
466 if (shc_eeprom_valid)
467 if (is_valid_ethaddr(header.mac_addr))
468 eth_env_set_enetaddr("ethaddr", header.mac_addr);
469 #endif
470
471 return 0;
472 }
473 #endif
474
475 #if defined(CONFIG_USB_ETHER) && \
476 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
board_eth_init(struct bd_info * bis)477 int board_eth_init(struct bd_info *bis)
478 {
479 return usb_eth_initialize(bis);
480 }
481 #endif
482
483 #if CONFIG_IS_ENABLED(BOOTSTAGE)
bosch_check_reset_pin(void)484 static void bosch_check_reset_pin(void)
485 {
486 if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
487 printf("Resetting ...\n");
488 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
489 disable_interrupts();
490 reset_cpu();
491 /*NOTREACHED*/
492 }
493 }
494
hang_bosch(const char * cause,int code)495 static void hang_bosch(const char *cause, int code)
496 {
497 int lv;
498
499 gpio_direction_input(RESET_GPIO);
500
501 /* Enable reset pin interrupt on falling edge */
502 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
503 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
504 enable_interrupts();
505
506 puts(cause);
507 for (;;) {
508 for (lv = 0; lv < code; lv++) {
509 bosch_check_reset_pin();
510 leds_set_failure(1);
511 __udelay(150 * 1000);
512 leds_set_failure(0);
513 __udelay(150 * 1000);
514 }
515 #if defined(BLINK_CODE)
516 __udelay(300 * 1000);
517 #endif
518 }
519 }
520
show_boot_progress(int val)521 void show_boot_progress(int val)
522 {
523 switch (val) {
524 case BOOTSTAGE_ID_NEED_RESET:
525 hang_bosch("need reset", 4);
526 break;
527 }
528 }
529 #endif
530
arch_preboot_os(void)531 void arch_preboot_os(void)
532 {
533 leds_set_finish();
534 }
535