1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2020 Broadcom.
4 *
5 */
6
7 #include <common.h>
8 #include <fdt_support.h>
9 #include <asm/io.h>
10 #include <asm/gic-v3.h>
11 #include <asm/global_data.h>
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
14 #include <asm/arch-bcmns3/bl33_info.h>
15 #include <dt-bindings/memory/bcm-ns3-mc.h>
16 #include <broadcom/chimp.h>
17
18 #define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
19
20 /*
21 * ns3_dram_bank - DDR bank details
22 *
23 * @start: DDR bank start address
24 * @len: DDR bank length
25 */
26 struct ns3_dram_bank {
27 u64 start[BCM_NS3_MAX_NR_BANKS];
28 u64 len[BCM_NS3_MAX_NR_BANKS];
29 };
30
31 /*
32 * ns3_dram_hdr - DDR header info
33 *
34 * @sig: DDR info signature
35 * @bank: DDR bank details
36 */
37 struct ns3_dram_hdr {
38 u32 sig;
39 struct ns3_dram_bank bank;
40 };
41
42 static struct mm_region ns3_mem_map[] = {
43 {
44 .virt = 0x0UL,
45 .phys = 0x0UL,
46 .size = 0x80000000UL,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 PTE_BLOCK_NON_SHARE |
49 PTE_BLOCK_PXN | PTE_BLOCK_UXN
50 }, {
51 .virt = BCM_NS3_MEM_START,
52 .phys = BCM_NS3_MEM_START,
53 .size = BCM_NS3_MEM_LEN,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
55 PTE_BLOCK_INNER_SHARE
56 }, {
57 .virt = BCM_NS3_BANK_1_MEM_START,
58 .phys = BCM_NS3_BANK_1_MEM_START,
59 .size = BCM_NS3_BANK_1_MEM_LEN,
60 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
61 PTE_BLOCK_INNER_SHARE
62 }, {
63 /* List terminator */
64 0,
65 }
66 };
67
68 struct mm_region *mem_map = ns3_mem_map;
69
70 DECLARE_GLOBAL_DATA_PTR;
71
72 /*
73 * Force the bl33_info to the data-section, as .bss will not be valid
74 * when save_boot_params is invoked.
75 */
76 struct bl33_info *bl33_info __section(".data");
77
78 /*
79 * Run modulo 256 checksum calculation and return the calculated checksum
80 */
checksum_calc(u8 * p,unsigned int len)81 static u8 checksum_calc(u8 *p, unsigned int len)
82 {
83 unsigned int i;
84 u8 chksum = 0;
85
86 for (i = 0; i < len; i++)
87 chksum += p[i];
88
89 return chksum;
90 }
91
92 /*
93 * This function parses the memory layout information from a reserved area in
94 * DDR, and then fix up the FDT before passing it to Linux.
95 *
96 * In the case of error, do nothing and the default memory layout in DT will
97 * be used
98 */
mem_info_parse_fixup(void * fdt)99 static int mem_info_parse_fixup(void *fdt)
100 {
101 struct ns3_dram_hdr hdr;
102 u32 *p32, i, nr_banks;
103 u64 *p64;
104
105 /* validate signature */
106 p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
107 hdr.sig = *p32;
108 if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
109 printf("DDR info signature 0x%x invalid\n", hdr.sig);
110 return -EINVAL;
111 }
112
113 /* run checksum test to validate data */
114 if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
115 printf("Checksum on DDR info failed\n");
116 return -EINVAL;
117 }
118
119 /* parse information for each bank */
120 nr_banks = 0;
121 for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
122 /* skip banks with a length of zero */
123 p64 = (u64 *)BANK_OFFSET(i);
124 if (*(p64 + 1) == 0)
125 continue;
126
127 hdr.bank.start[i] = *p64;
128 hdr.bank.len[i] = *(p64 + 1);
129
130 printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
131 hdr.bank.start[i] + hdr.bank.len[i] - 1);
132 nr_banks++;
133 }
134
135 if (!nr_banks) {
136 printf("No DDR banks detected\n");
137 return -ENOMEM;
138 }
139
140 return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
141 nr_banks);
142 }
143
board_init(void)144 int board_init(void)
145 {
146 /* Setup memory using "memory" node from DTB */
147 if (fdtdec_setup_mem_size_base() != 0)
148 return -EINVAL;
149 fdtdec_setup_memory_banksize();
150
151 if (bl33_info->version != BL33_INFO_VERSION)
152 printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
153
154 return 0;
155 }
156
board_late_init(void)157 int board_late_init(void)
158 {
159 return 0;
160 }
161
dram_init(void)162 int dram_init(void)
163 {
164 /*
165 * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
166 * So that relocation happens with in the last 16MB memory.
167 */
168 gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
169 gd->ram_size = (unsigned long)SZ_16M;
170
171 return 0;
172 }
173
dram_init_banksize(void)174 int dram_init_banksize(void)
175 {
176 gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
177 gd->bd->bi_dram[0].size = SZ_16M;
178
179 return 0;
180 }
181
182 /* Limit RAM used by U-Boot to the DDR first bank End region */
board_get_usable_ram_top(ulong total_size)183 ulong board_get_usable_ram_top(ulong total_size)
184 {
185 return BCM_NS3_MEM_END;
186 }
187
reset_cpu(void)188 void reset_cpu(void)
189 {
190 /* Perform a level 3 reset */
191 psci_system_reset2(3, 0);
192 }
193
194 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * fdt,struct bd_info * bd)195 int ft_board_setup(void *fdt, struct bd_info *bd)
196 {
197 u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
198
199 /* FIXME: Need to call gic_lpi_tables_init correctly now */
200 printf("%s: failed to init gic-lpi-tables\n", __func__);
201
202 /*
203 * Check for chimp handshake status.
204 * Zero timeout value will actually fall to default timeout.
205 *
206 * System boot is independent of chimp handshake.
207 * chimp handshake failure is not a catastrophic error.
208 * Hence continue booting if chimp handshake fails.
209 */
210 chimp_handshake_status_optee(0, &chimp_hs);
211 if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
212 printf("ChiMP handshake successful\n");
213 else
214 printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
215
216 return mem_info_parse_fixup(fdt);
217 }
218 #endif /* CONFIG_OF_BOARD_SETUP */
219