1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Compulab, Ltd.
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <init.h>
9 #include <spl.h>
10 #include <i2c.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/ddr_defs.h>
13 #include <asm/gpio.h>
14 #include <power/pmic.h>
15 #include <power/tps65218.h>
16 #include "board.h"
17
18 const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
19 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
20 const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
21 const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
22
23 const struct ctrl_ioregs ioregs_ddr3 = {
24 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
25 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
26 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
27 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
28 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
29 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
30 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
31 .emif_sdram_config_ext = 0x0143,
32 };
33
34 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
35 struct emif_regs ddr3_emif_regs = {
36 .sdram_config = 0x638413B2,
37 .ref_ctrl = 0x00000C30,
38 .sdram_tim1 = 0xEAAAD4DB,
39 .sdram_tim2 = 0x266B7FDA,
40 .sdram_tim3 = 0x107F8678,
41 .read_idle_ctrl = 0x00050000,
42 .zq_config = 0x50074BE4,
43 .temp_alert_config = 0x0,
44 .emif_ddr_phy_ctlr_1 = 0x0E004008,
45 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
46 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
47 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
48 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
49 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
50 .emif_rd_wr_exec_thresh = 0x80000405,
51 .emif_prio_class_serv_map = 0x80000001,
52 .emif_connect_id_serv_1_map = 0x80000094,
53 .emif_connect_id_serv_2_map = 0x00000000,
54 .emif_cos_config = 0x000FFFFF
55 };
56
57 const u32 ext_phy_ctrl_const_base_ddr3[] = {
58 0x00000000,
59 0x00000044,
60 0x00000044,
61 0x00000046,
62 0x00000046,
63 0x00000000,
64 0x00000059,
65 0x00000077,
66 0x00000093,
67 0x000000A8,
68 0x00000000,
69 0x00000019,
70 0x00000037,
71 0x00000053,
72 0x00000068,
73 0x00000000,
74 0x0,
75 0x0,
76 0x40000000,
77 0x08102040
78 };
79
emif_get_ext_phy_ctrl_const_regs(const u32 ** regs,u32 * size)80 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
81 {
82 *regs = ext_phy_ctrl_const_base_ddr3;
83 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
84 }
85
get_dpll_ddr_params(void)86 const struct dpll_params *get_dpll_ddr_params(void)
87 {
88 return &dpll_ddr;
89 }
90
get_dpll_mpu_params(void)91 const struct dpll_params *get_dpll_mpu_params(void)
92 {
93 return &dpll_mpu;
94 }
95
get_dpll_core_params(void)96 const struct dpll_params *get_dpll_core_params(void)
97 {
98 return &dpll_core;
99 }
100
get_dpll_per_params(void)101 const struct dpll_params *get_dpll_per_params(void)
102 {
103 return &dpll_per;
104 }
105
scale_vcores(void)106 void scale_vcores(void)
107 {
108 set_i2c_pin_mux();
109 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
110 if (i2c_probe(TPS65218_CHIP_PM))
111 return;
112
113 tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
114 tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
115 }
116
sdram_init(void)117 void sdram_init(void)
118 {
119 unsigned long ram_size;
120
121 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
122 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
123 if (ram_size == 0x80000000 ||
124 ram_size == 0x40000000 ||
125 ram_size == 0x20000000)
126 return;
127
128 ddr3_emif_regs.sdram_config = 0x638453B2;
129 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
130 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
131 if (ram_size == 0x08000000)
132 return;
133
134 hang();
135 }
136