1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <adc.h>
8 #include <log.h>
9 #include <net.h>
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <bootm.h>
16 #include <clk.h>
17 #include <config.h>
18 #include <dm.h>
19 #include <dm/device.h>
20 #include <dm/uclass.h>
21 #include <env.h>
22 #include <env_internal.h>
23 #include <g_dnl.h>
24 #include <generic-phy.h>
25 #include <hang.h>
26 #include <i2c.h>
27 #include <i2c_eeprom.h>
28 #include <init.h>
29 #include <led.h>
30 #include <memalign.h>
31 #include <misc.h>
32 #include <mtd.h>
33 #include <mtd_node.h>
34 #include <netdev.h>
35 #include <phy.h>
36 #include <linux/bitops.h>
37 #include <linux/delay.h>
38 #include <power/regulator.h>
39 #include <remoteproc.h>
40 #include <reset.h>
41 #include <syscon.h>
42 #include <usb.h>
43 #include <usb/dwc2_udc.h>
44 #include <watchdog.h>
45 #include <dm/ofnode.h>
46 #include "../../st/common/stpmic1.h"
47
48 /* SYSCFG registers */
49 #define SYSCFG_BOOTR 0x00
50 #define SYSCFG_PMCSETR 0x04
51 #define SYSCFG_IOCTRLSETR 0x18
52 #define SYSCFG_ICNR 0x1C
53 #define SYSCFG_CMPCR 0x20
54 #define SYSCFG_CMPENSETR 0x24
55 #define SYSCFG_PMCCLRR 0x44
56
57 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
58 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
59
60 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
61 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
62 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
63 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
64 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
65
66 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
67 #define SYSCFG_CMPCR_READY BIT(8)
68
69 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
70
71 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
72 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
73
74 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
75
76 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
77 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
78 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
79 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
80
81 /*
82 * Get a global data pointer
83 */
84 DECLARE_GLOBAL_DATA_PTR;
85
86 #define KS_CCR 0x08
87 #define KS_CCR_EEPROM BIT(9)
88 #define KS_BE0 BIT(12)
89 #define KS_BE1 BIT(13)
90 #define KS_CIDER 0xC0
91 #define CIDER_ID 0x8870
92
setup_mac_address(void)93 int setup_mac_address(void)
94 {
95 unsigned char enetaddr[6];
96 bool skip_eth0 = false;
97 bool skip_eth1 = false;
98 struct udevice *dev;
99 int off, ret;
100
101 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
102 if (ret) /* ethaddr is already set */
103 skip_eth0 = true;
104
105 off = fdt_path_offset(gd->fdt_blob, "ethernet1");
106 if (off < 0) {
107 /* ethernet1 is not present in the system */
108 skip_eth1 = true;
109 goto out_set_ethaddr;
110 }
111
112 ret = eth_env_get_enetaddr("eth1addr", enetaddr);
113 if (ret) {
114 /* eth1addr is already set */
115 skip_eth1 = true;
116 goto out_set_ethaddr;
117 }
118
119 ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
120 if (ret)
121 goto out_set_ethaddr;
122
123 /*
124 * KS8851 with EEPROM may use custom MAC from EEPROM, read
125 * out the KS8851 CCR register to determine whether EEPROM
126 * is present. If EEPROM is present, it must contain valid
127 * MAC address.
128 */
129 u32 reg, cider, ccr;
130 reg = fdt_get_base_address(gd->fdt_blob, off);
131 if (!reg)
132 goto out_set_ethaddr;
133
134 writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
135 cider = readw(reg);
136 if ((cider & 0xfff0) != CIDER_ID) {
137 skip_eth1 = true;
138 goto out_set_ethaddr;
139 }
140
141 writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
142 ccr = readw(reg);
143 if (ccr & KS_CCR_EEPROM) {
144 skip_eth1 = true;
145 goto out_set_ethaddr;
146 }
147
148 out_set_ethaddr:
149 if (skip_eth0 && skip_eth1)
150 return 0;
151
152 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
153 if (off < 0) {
154 printf("%s: No eeprom0 path offset\n", __func__);
155 return off;
156 }
157
158 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
159 if (ret) {
160 printf("Cannot find EEPROM!\n");
161 return ret;
162 }
163
164 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
165 if (ret) {
166 printf("Error reading configuration EEPROM!\n");
167 return ret;
168 }
169
170 if (is_valid_ethaddr(enetaddr)) {
171 if (!skip_eth0)
172 eth_env_set_enetaddr("ethaddr", enetaddr);
173
174 enetaddr[5]++;
175 if (!skip_eth1)
176 eth_env_set_enetaddr("eth1addr", enetaddr);
177 }
178
179 return 0;
180 }
181
checkboard(void)182 int checkboard(void)
183 {
184 char *mode;
185 const char *fdt_compat;
186 int fdt_compat_len;
187
188 if (IS_ENABLED(CONFIG_TFABOOT))
189 mode = "trusted";
190 else
191 mode = "basic";
192
193 printf("Board: stm32mp1 in %s mode", mode);
194 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
195 &fdt_compat_len);
196 if (fdt_compat && fdt_compat_len)
197 printf(" (%s)", fdt_compat);
198 puts("\n");
199
200 return 0;
201 }
202
203 #ifdef CONFIG_BOARD_EARLY_INIT_F
204 static u8 brdcode __section("data");
205 static u8 ddr3code __section("data");
206 static u8 somcode __section("data");
207 static u32 opp_voltage_mv __section(".data");
208
board_get_coding_straps(void)209 static void board_get_coding_straps(void)
210 {
211 struct gpio_desc gpio[4];
212 ofnode node;
213 int i, ret;
214
215 node = ofnode_path("/config");
216 if (!ofnode_valid(node)) {
217 printf("%s: no /config node?\n", __func__);
218 return;
219 }
220
221 brdcode = 0;
222 ddr3code = 0;
223 somcode = 0;
224
225 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
226 gpio, ARRAY_SIZE(gpio),
227 GPIOD_IS_IN);
228 for (i = 0; i < ret; i++)
229 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
230
231 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
232 gpio, ARRAY_SIZE(gpio),
233 GPIOD_IS_IN);
234 for (i = 0; i < ret; i++)
235 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
236
237 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
238 gpio, ARRAY_SIZE(gpio),
239 GPIOD_IS_IN);
240 for (i = 0; i < ret; i++)
241 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
242
243 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
244 somcode, ddr3code, brdcode);
245 }
246
board_stm32mp1_ddr_config_name_match(struct udevice * dev,const char * name)247 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
248 const char *name)
249 {
250 if (ddr3code == 1 &&
251 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
252 return 0;
253
254 if (ddr3code == 2 &&
255 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
256 return 0;
257
258 if (ddr3code == 3 &&
259 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
260 return 0;
261
262 return -EINVAL;
263 }
264
board_vddcore_init(u32 voltage_mv)265 void board_vddcore_init(u32 voltage_mv)
266 {
267 if (IS_ENABLED(CONFIG_SPL_BUILD))
268 opp_voltage_mv = voltage_mv;
269 }
270
board_early_init_f(void)271 int board_early_init_f(void)
272 {
273 if (IS_ENABLED(CONFIG_SPL_BUILD))
274 stpmic1_init(opp_voltage_mv);
275 board_get_coding_straps();
276
277 return 0;
278 }
279
280 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)281 int board_fit_config_name_match(const char *name)
282 {
283 const char *compat;
284 char test[128];
285
286 compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
287
288 snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
289 compat, somcode, brdcode);
290
291 if (!strcmp(name, test))
292 return 0;
293
294 return -EINVAL;
295 }
296 #endif
297 #endif
298
board_key_check(void)299 static void board_key_check(void)
300 {
301 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
302 ofnode node;
303 struct gpio_desc gpio;
304 enum forced_boot_mode boot_mode = BOOT_NORMAL;
305
306 node = ofnode_path("/config");
307 if (!ofnode_valid(node)) {
308 debug("%s: no /config node?\n", __func__);
309 return;
310 }
311 #ifdef CONFIG_FASTBOOT
312 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
313 &gpio, GPIOD_IS_IN)) {
314 debug("%s: could not find a /config/st,fastboot-gpios\n",
315 __func__);
316 } else {
317 if (dm_gpio_get_value(&gpio)) {
318 puts("Fastboot key pressed, ");
319 boot_mode = BOOT_FASTBOOT;
320 }
321
322 dm_gpio_free(NULL, &gpio);
323 }
324 #endif
325 #ifdef CONFIG_CMD_STM32PROG
326 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
327 &gpio, GPIOD_IS_IN)) {
328 debug("%s: could not find a /config/st,stm32prog-gpios\n",
329 __func__);
330 } else {
331 if (dm_gpio_get_value(&gpio)) {
332 puts("STM32Programmer key pressed, ");
333 boot_mode = BOOT_STM32PROG;
334 }
335 dm_gpio_free(NULL, &gpio);
336 }
337 #endif
338
339 if (boot_mode != BOOT_NORMAL) {
340 puts("entering download mode...\n");
341 clrsetbits_le32(TAMP_BOOT_CONTEXT,
342 TAMP_BOOT_FORCED_MASK,
343 boot_mode);
344 }
345 #endif
346 }
347
348 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
349
350 #include <usb/dwc2_udc.h>
g_dnl_board_usb_cable_connected(void)351 int g_dnl_board_usb_cable_connected(void)
352 {
353 struct udevice *dwc2_udc_otg;
354 int ret;
355
356 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
357 DM_DRIVER_GET(dwc2_udc_otg),
358 &dwc2_udc_otg);
359 if (!ret)
360 debug("dwc2_udc_otg init failed\n");
361
362 return dwc2_udc_B_session_valid(dwc2_udc_otg);
363 }
364
365 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
366 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
367
g_dnl_bind_fixup(struct usb_device_descriptor * dev,const char * name)368 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
369 {
370 if (!strcmp(name, "usb_dnl_dfu"))
371 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
372 else if (!strcmp(name, "usb_dnl_fastboot"))
373 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
374 &dev->idProduct);
375 else
376 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
377
378 return 0;
379 }
380
381 #endif /* CONFIG_USB_GADGET */
382
383 #ifdef CONFIG_LED
get_led(struct udevice ** dev,char * led_string)384 static int get_led(struct udevice **dev, char *led_string)
385 {
386 const char *led_name;
387 int ret;
388
389 led_name = ofnode_conf_read_str(led_string);
390 if (!led_name) {
391 pr_debug("%s: could not find %s config string\n",
392 __func__, led_string);
393 return -ENOENT;
394 }
395 ret = led_get_by_label(led_name, dev);
396 if (ret) {
397 debug("%s: get=%d\n", __func__, ret);
398 return ret;
399 }
400
401 return 0;
402 }
403
setup_led(enum led_state_t cmd)404 static int setup_led(enum led_state_t cmd)
405 {
406 struct udevice *dev;
407 int ret;
408
409 ret = get_led(&dev, "u-boot,boot-led");
410 if (ret)
411 return ret;
412
413 ret = led_set_state(dev, cmd);
414 return ret;
415 }
416 #endif
417
led_error_blink(u32 nb_blink)418 static void __maybe_unused led_error_blink(u32 nb_blink)
419 {
420 #ifdef CONFIG_LED
421 int ret;
422 struct udevice *led;
423 u32 i;
424 #endif
425
426 if (!nb_blink)
427 return;
428
429 #ifdef CONFIG_LED
430 ret = get_led(&led, "u-boot,error-led");
431 if (!ret) {
432 /* make u-boot,error-led blinking */
433 /* if U32_MAX and 125ms interval, for 17.02 years */
434 for (i = 0; i < 2 * nb_blink; i++) {
435 led_set_state(led, LEDST_TOGGLE);
436 mdelay(125);
437 WATCHDOG_RESET();
438 }
439 }
440 #endif
441
442 /* infinite: the boot process must be stopped */
443 if (nb_blink == U32_MAX)
444 hang();
445 }
446
sysconf_init(void)447 static void sysconf_init(void)
448 {
449 #ifndef CONFIG_TFABOOT
450 u8 *syscfg;
451 #ifdef CONFIG_DM_REGULATOR
452 struct udevice *pwr_dev;
453 struct udevice *pwr_reg;
454 struct udevice *dev;
455 int ret;
456 u32 otp = 0;
457 #endif
458 u32 bootr;
459
460 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
461
462 /* interconnect update : select master using the port 1 */
463 /* LTDC = AXI_M9 */
464 /* GPU = AXI_M8 */
465 /* today information is hardcoded in U-Boot */
466 writel(BIT(9), syscfg + SYSCFG_ICNR);
467
468 /* disable Pull-Down for boot pin connected to VDD */
469 bootr = readl(syscfg + SYSCFG_BOOTR);
470 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
471 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
472 writel(bootr, syscfg + SYSCFG_BOOTR);
473
474 #ifdef CONFIG_DM_REGULATOR
475 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
476 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
477 * The customer will have to disable this for low frequencies
478 * or if AFMUX is selected but the function not used, typically for
479 * TRACE. Otherwise, impact on power consumption.
480 *
481 * WARNING:
482 * enabling High Speed mode while VDD>2.7V
483 * with the OTP product_below_2v5 (OTP 18, BIT 13)
484 * erroneously set to 1 can damage the IC!
485 * => U-Boot set the register only if VDD < 2.7V (in DT)
486 * but this value need to be consistent with board design
487 */
488 ret = uclass_get_device_by_driver(UCLASS_PMIC,
489 DM_DRIVER_GET(stm32mp_pwr_pmic),
490 &pwr_dev);
491 if (!ret) {
492 ret = uclass_get_device_by_driver(UCLASS_MISC,
493 DM_DRIVER_GET(stm32mp_bsec),
494 &dev);
495 if (ret) {
496 pr_err("Can't find stm32mp_bsec driver\n");
497 return;
498 }
499
500 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
501 if (ret > 0)
502 otp = otp & BIT(13);
503
504 /* get VDD = vdd-supply */
505 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
506 &pwr_reg);
507
508 /* check if VDD is Low Voltage */
509 if (!ret) {
510 if (regulator_get_value(pwr_reg) < 2700000) {
511 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
512 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
513 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
514 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
515 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
516 syscfg + SYSCFG_IOCTRLSETR);
517
518 if (!otp)
519 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
520 } else {
521 if (otp)
522 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
523 }
524 } else {
525 debug("VDD unknown");
526 }
527 }
528 #endif
529
530 /* activate automatic I/O compensation
531 * warning: need to ensure CSI enabled and ready in clock driver
532 */
533 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
534
535 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
536 ;
537 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
538 #endif
539 }
540
board_init_fmc2(void)541 static void board_init_fmc2(void)
542 {
543 #define STM32_FMC2_BCR1 0x0
544 #define STM32_FMC2_BTR1 0x4
545 #define STM32_FMC2_BWTR1 0x104
546 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
547 #define STM32_FMC2_BCRx_FMCEN BIT(31)
548 #define STM32_FMC2_BCRx_WREN BIT(12)
549 #define STM32_FMC2_BCRx_RSVD BIT(7)
550 #define STM32_FMC2_BCRx_FACCEN BIT(6)
551 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
552 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
553 #define STM32_FMC2_BCRx_MUXEN BIT(1)
554 #define STM32_FMC2_BCRx_MBKEN BIT(0)
555 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
556 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
557 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
558 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
559 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
560 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
561
562 #define RCC_MP_AHB6RSTCLRR 0x218
563 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
564 #define RCC_MP_AHB6ENSETR 0x19c
565 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
566
567 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
568 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
569 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
570 STM32_FMC2_BCRx_MBKEN;
571 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
572 STM32_FMC2_BTRx_BUSTURN(2) |
573 STM32_FMC2_BTRx_DATAST(0x22) |
574 STM32_FMC2_BTRx_ADDHLD(2) |
575 STM32_FMC2_BTRx_ADDSET(2);
576
577 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
578 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
579 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
580
581 /* KS8851-16MLL -- Muxed mode */
582 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
583 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
584 /* AS7C34098 SRAM on X11 -- Muxed mode */
585 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
586 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
587
588 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
589 }
590
591 /* board dependent setup after realloc */
board_init(void)592 int board_init(void)
593 {
594 board_key_check();
595
596 #ifdef CONFIG_DM_REGULATOR
597 regulators_enable_boot_on(_DEBUG);
598 #endif
599
600 sysconf_init();
601
602 board_init_fmc2();
603
604 if (CONFIG_IS_ENABLED(LED))
605 led_default_state();
606
607 return 0;
608 }
609
board_late_init(void)610 int board_late_init(void)
611 {
612 char *boot_device;
613 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
614 const void *fdt_compat;
615 int fdt_compat_len;
616
617 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
618 &fdt_compat_len);
619 if (fdt_compat && fdt_compat_len) {
620 if (strncmp(fdt_compat, "st,", 3) != 0)
621 env_set("board_name", fdt_compat);
622 else
623 env_set("board_name", fdt_compat + 3);
624 }
625 #endif
626
627 /* Check the boot-source to disable bootdelay */
628 boot_device = env_get("boot_device");
629 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
630 env_set("bootdelay", "0");
631
632 #ifdef CONFIG_BOARD_EARLY_INIT_F
633 env_set_ulong("dh_som_rev", somcode);
634 env_set_ulong("dh_board_rev", brdcode);
635 env_set_ulong("dh_ddr3_code", ddr3code);
636 #endif
637
638 return 0;
639 }
640
board_quiesce_devices(void)641 void board_quiesce_devices(void)
642 {
643 #ifdef CONFIG_LED
644 setup_led(LEDST_OFF);
645 #endif
646 }
647
648 /* eth init function : weak called in eqos driver */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)649 int board_interface_eth_init(struct udevice *dev,
650 phy_interface_t interface_type)
651 {
652 u8 *syscfg;
653 u32 value;
654 bool eth_clk_sel_reg = false;
655 bool eth_ref_clk_sel_reg = false;
656
657 /* Gigabit Ethernet 125MHz clock selection. */
658 eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
659
660 /* Ethernet 50Mhz RMII clock selection */
661 eth_ref_clk_sel_reg =
662 dev_read_bool(dev, "st,eth-ref-clk-sel");
663
664 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
665
666 if (!syscfg)
667 return -ENODEV;
668
669 switch (interface_type) {
670 case PHY_INTERFACE_MODE_MII:
671 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
672 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
673 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
674 break;
675 case PHY_INTERFACE_MODE_GMII:
676 if (eth_clk_sel_reg)
677 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
678 SYSCFG_PMCSETR_ETH_CLK_SEL;
679 else
680 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
681 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
682 break;
683 case PHY_INTERFACE_MODE_RMII:
684 if (eth_ref_clk_sel_reg)
685 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
686 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
687 else
688 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
689 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
690 break;
691 case PHY_INTERFACE_MODE_RGMII:
692 case PHY_INTERFACE_MODE_RGMII_ID:
693 case PHY_INTERFACE_MODE_RGMII_RXID:
694 case PHY_INTERFACE_MODE_RGMII_TXID:
695 if (eth_clk_sel_reg)
696 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
697 SYSCFG_PMCSETR_ETH_CLK_SEL;
698 else
699 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
700 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
701 break;
702 default:
703 debug("%s: Do not manage %d interface\n",
704 __func__, interface_type);
705 /* Do not manage others interfaces */
706 return -EINVAL;
707 }
708
709 /* clear and set ETH configuration bits */
710 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
711 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
712 syscfg + SYSCFG_PMCCLRR);
713 writel(value, syscfg + SYSCFG_PMCSETR);
714
715 return 0;
716 }
717
718 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)719 int ft_board_setup(void *blob, struct bd_info *bd)
720 {
721 return 0;
722 }
723 #endif
724
board_copro_image_process(ulong fw_image,size_t fw_size)725 static void board_copro_image_process(ulong fw_image, size_t fw_size)
726 {
727 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
728
729 if (!rproc_is_initialized())
730 if (rproc_init()) {
731 printf("Remote Processor %d initialization failed\n",
732 id);
733 return;
734 }
735
736 ret = rproc_load(id, fw_image, fw_size);
737 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
738 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
739
740 if (!ret) {
741 rproc_start(id);
742 env_set("copro_state", "booted");
743 }
744 }
745
746 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
747