1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2017 Tuomas Tynkkynen
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <init.h>
11 #include <log.h>
12 #include <virtio_types.h>
13 #include <virtio.h>
14
15 #ifdef CONFIG_ARM64
16 #include <asm/armv8/mmu.h>
17
18 static struct mm_region qemu_arm64_mem_map[] = {
19 {
20 /* Flash */
21 .virt = 0x00000000UL,
22 .phys = 0x00000000UL,
23 .size = 0x08000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE
26 }, {
27 /* Lowmem peripherals */
28 .virt = 0x08000000UL,
29 .phys = 0x08000000UL,
30 .size = 0x38000000,
31 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 PTE_BLOCK_NON_SHARE |
33 PTE_BLOCK_PXN | PTE_BLOCK_UXN
34 }, {
35 /* RAM */
36 .virt = 0x40000000UL,
37 .phys = 0x40000000UL,
38 .size = 255UL * SZ_1G,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 PTE_BLOCK_INNER_SHARE
41 }, {
42 /* Highmem PCI-E ECAM memory area */
43 .virt = 0x4010000000ULL,
44 .phys = 0x4010000000ULL,
45 .size = 0x10000000,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 PTE_BLOCK_NON_SHARE |
48 PTE_BLOCK_PXN | PTE_BLOCK_UXN
49 }, {
50 /* Highmem PCI-E MMIO memory area */
51 .virt = 0x8000000000ULL,
52 .phys = 0x8000000000ULL,
53 .size = 0x8000000000ULL,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
55 PTE_BLOCK_NON_SHARE |
56 PTE_BLOCK_PXN | PTE_BLOCK_UXN
57 }, {
58 /* List terminator */
59 0,
60 }
61 };
62
63 struct mm_region *mem_map = qemu_arm64_mem_map;
64 #endif
65
board_init(void)66 int board_init(void)
67 {
68 return 0;
69 }
70
board_late_init(void)71 int board_late_init(void)
72 {
73 /*
74 * Make sure virtio bus is enumerated so that peripherals
75 * on the virtio bus can be discovered by their drivers
76 */
77 virtio_init();
78
79 return 0;
80 }
81
dram_init(void)82 int dram_init(void)
83 {
84 if (fdtdec_setup_mem_size_base() != 0)
85 return -EINVAL;
86
87 return 0;
88 }
89
dram_init_banksize(void)90 int dram_init_banksize(void)
91 {
92 fdtdec_setup_memory_banksize();
93
94 return 0;
95 }
96
board_fdt_blob_setup(int * err)97 void *board_fdt_blob_setup(int *err)
98 {
99 *err = 0;
100 /* QEMU loads a generated DTB for us at the start of RAM. */
101 return (void *)CONFIG_SYS_SDRAM_BASE;
102 }
103
enable_caches(void)104 void enable_caches(void)
105 {
106 icache_enable();
107 dcache_enable();
108 }
109
110 #if defined(CONFIG_EFI_RNG_PROTOCOL)
111 #include <efi_loader.h>
112 #include <efi_rng.h>
113
114 #include <dm/device-internal.h>
115
platform_get_rng_device(struct udevice ** dev)116 efi_status_t platform_get_rng_device(struct udevice **dev)
117 {
118 int ret;
119 efi_status_t status = EFI_DEVICE_ERROR;
120 struct udevice *bus, *devp;
121
122 for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
123 uclass_next_device(&bus)) {
124 for (device_find_first_child(bus, &devp); devp;
125 device_find_next_child(&devp)) {
126 if (device_get_uclass_id(devp) == UCLASS_RNG) {
127 *dev = devp;
128 status = EFI_SUCCESS;
129 break;
130 }
131 }
132 }
133
134 if (status != EFI_SUCCESS) {
135 debug("No rng device found\n");
136 return EFI_DEVICE_ERROR;
137 }
138
139 if (*dev) {
140 ret = device_probe(*dev);
141 if (ret)
142 return EFI_DEVICE_ERROR;
143 } else {
144 debug("Couldn't get child device\n");
145 return EFI_DEVICE_ERROR;
146 }
147
148 return EFI_SUCCESS;
149 }
150 #endif /* CONFIG_EFI_RNG_PROTOCOL */
151
152 #ifdef CONFIG_ARM64
153 #define __W "w"
154 #else
155 #define __W
156 #endif
157
flash_read8(void * addr)158 u8 flash_read8(void *addr)
159 {
160 u8 ret;
161
162 asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
163 return ret;
164 }
165
flash_read16(void * addr)166 u16 flash_read16(void *addr)
167 {
168 u16 ret;
169
170 asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
171 return ret;
172 }
173
flash_read32(void * addr)174 u32 flash_read32(void *addr)
175 {
176 u32 ret;
177
178 asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
179 return ret;
180 }
181
flash_write8(u8 value,void * addr)182 void flash_write8(u8 value, void *addr)
183 {
184 asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
185 }
186
flash_write16(u16 value,void * addr)187 void flash_write16(u16 value, void *addr)
188 {
189 asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
190 }
191
flash_write32(u32 value,void * addr)192 void flash_write32(u32 value, void *addr)
193 {
194 asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
195 }
196