1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #ifndef CONFIG_ARMV7_NONSEC
11 #error " Deep sleep needs non-secure mode support. "
12 #else
13 #include <asm/secure.h>
14 #endif
15 #include <asm/armv7.h>
16
17 #if defined(CONFIG_ARCH_LS1021A)
18 #include <asm/arch/immap_ls102xa.h>
19 #endif
20
21 #include "sleep.h"
22 #ifdef CONFIG_U_QE
23 #include <fsl_qe.h>
24 #endif
25
26 DECLARE_GLOBAL_DATA_PTR;
27
board_mem_sleep_setup(void)28 void __weak board_mem_sleep_setup(void)
29 {
30 }
31
board_sleep_prepare(void)32 void __weak board_sleep_prepare(void)
33 {
34 }
35
is_warm_boot(void)36 bool is_warm_boot(void)
37 {
38 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
39
40 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
41 return 1;
42
43 return 0;
44 }
45
fsl_dp_disable_console(void)46 void fsl_dp_disable_console(void)
47 {
48 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
49 }
50
51 /*
52 * When wakeup from deep sleep, the first 128 bytes space
53 * will be used to do DDR training which corrupts the data
54 * in there. This function will restore them.
55 */
dp_ddr_restore(void)56 static void dp_ddr_restore(void)
57 {
58 u64 *src, *dst;
59 int i;
60 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
61
62 /* get the address of ddr date from SPARECR3 */
63 src = (u64 *)in_le32(&scfg->sparecr[2]);
64 dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
65
66 for (i = 0; i < DDR_BUFF_LEN / 8; i++)
67 *dst++ = *src++;
68 }
69
70 #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
ls1_psci_resume_fixup(void)71 void ls1_psci_resume_fixup(void)
72 {
73 u32 tmp;
74 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
75
76 #ifdef QIXIS_BASE
77 void *qixis_base = (void *)QIXIS_BASE;
78
79 /* Pull on PCIe RST# */
80 out_8(qixis_base + QIXIS_RST_FORCE_3, 0);
81
82 /* disable deep sleep signals in FPGA */
83 tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
84 tmp &= ~QIXIS_PWR_CTL2_PCTL;
85 out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
86 #endif
87
88 /* Disable wakeup interrupt during deep sleep */
89 out_be32(&scfg->pmcintecr, 0);
90 /* Clear PMC interrupt status */
91 out_be32(&scfg->pmcintsr, 0xffffffff);
92
93 /* Disable Warm Device Reset */
94 tmp = in_be32(&scfg->dpslpcr);
95 tmp &= ~SCFG_DPSLPCR_WDRR_EN;
96 out_be32(&scfg->dpslpcr, tmp);
97 }
98 #endif
99
dp_resume_prepare(void)100 static void dp_resume_prepare(void)
101 {
102 dp_ddr_restore();
103 board_sleep_prepare();
104 armv7_init_nonsec();
105 #ifdef CONFIG_U_QE
106 u_qe_resume();
107 #endif
108 #if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
109 ls1_psci_resume_fixup();
110 #endif
111 }
112
fsl_dp_resume(void)113 int fsl_dp_resume(void)
114 {
115 u32 start_addr;
116 void (*kernel_resume)(void);
117 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
118
119 if (!is_warm_boot())
120 return 0;
121
122 dp_resume_prepare();
123
124 /* Get the entry address and jump to kernel */
125 start_addr = in_le32(&scfg->sparecr[3]);
126 debug("Entry address is 0x%08x\n", start_addr);
127 kernel_resume = (void (*)(void))start_addr;
128 secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
129
130 return 0;
131 }
132